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| author | Peter De Schrijver <pdeschrijver@nvidia.com> | 2012-01-09 09:35:11 +0400 |
|---|---|---|
| committer | Olof Johansson <olof@lixom.net> | 2012-02-06 21:16:15 +0400 |
| commit | 4fccf75ba3bee0bb3be7828caa03625d4ac100a2 (patch) | |
| tree | ac2445c017187a1f68fbf642c1712706c0903c0b /arch/arm/mach-tegra/clock.h | |
| parent | caa4868ee07029e60450909960652b96a50ebfbd (diff) | |
| download | linux-4fccf75ba3bee0bb3be7828caa03625d4ac100a2.tar.xz | |
ARM: tegra: add support for new clock framework features
Add support for new clock framework features implemented in tegra30.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/mach-tegra/clock.h')
| -rw-r--r-- | arch/arm/mach-tegra/clock.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/clock.h b/arch/arm/mach-tegra/clock.h index 5c44106616c5..18f8b857361d 100644 --- a/arch/arm/mach-tegra/clock.h +++ b/arch/arm/mach-tegra/clock.h @@ -24,6 +24,8 @@ #include <linux/list.h> #include <linux/spinlock.h> +#include <mach/clk.h> + #define DIV_BUS (1 << 0) #define DIV_U71 (1 << 1) #define DIV_U71_FIXED (1 << 2) @@ -39,7 +41,16 @@ #define PERIPH_MANUAL_RESET (1 << 12) #define PLL_ALT_MISC_REG (1 << 13) #define PLLU (1 << 14) +#define PLLX (1 << 15) +#define MUX_PWM (1 << 16) +#define MUX8 (1 << 17) +#define DIV_U71_UART (1 << 18) +#define MUX_CLK_OUT (1 << 19) +#define PLLM (1 << 20) +#define DIV_U71_INT (1 << 21) +#define DIV_U71_IDLE (1 << 22) #define ENABLE_ON_INIT (1 << 28) +#define PERIPH_ON_APB (1 << 29) struct clk; @@ -65,6 +76,8 @@ struct clk_ops { int (*set_rate)(struct clk *, unsigned long); long (*round_rate)(struct clk *, unsigned long); void (*reset)(struct clk *, bool); + int (*clk_cfg_ex)(struct clk *, + enum tegra_clk_ex_param, u32); }; enum clk_state { @@ -114,6 +127,7 @@ struct clk { unsigned long vco_max; const struct clk_pll_freq_table *freq_table; int lock_delay; + unsigned long fixed_rate; } pll; struct { u32 sel; |