diff options
| author | Mark Brown <broonie@sirena.org.uk> | 2008-03-04 13:14:23 +0300 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2008-04-19 14:29:03 +0400 |
| commit | 60bfe7fa3dc13fe90d273371b65ae3ec89583c52 (patch) | |
| tree | 8ba51a09944c0e7e3b0d7bef2c20a15df4c673c1 /arch/arm/mach-pxa/pxa3xx.c | |
| parent | 27b98a671ff4cda89ba279452115000da59a9067 (diff) | |
| download | linux-60bfe7fa3dc13fe90d273371b65ae3ec89583c52.tar.xz | |
[ARM] 4832/2: Support AC97CLK on PXA3xx via the clock API
The AC97 clock rate on PXA3xx is generated with a configurable divider
from sys_pll.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: eric miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-pxa/pxa3xx.c')
| -rw-r--r-- | arch/arm/mach-pxa/pxa3xx.c | 30 |
1 files changed, 28 insertions, 2 deletions
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c index 54c9e8371a21..93f3236b4100 100644 --- a/arch/arm/mach-pxa/pxa3xx.c +++ b/arch/arm/mach-pxa/pxa3xx.c @@ -110,6 +110,25 @@ unsigned int pxa3xx_get_memclk_frequency_10khz(void) } /* + * Return the current AC97 clock frequency. + */ +static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk) +{ + unsigned long rate = 312000000; + unsigned long ac97_div; + + ac97_div = AC97_DIV; + + /* This may loose precision for some rates but won't for the + * standard 24.576MHz. + */ + rate /= (ac97_div >> 12) & 0x7fff; + rate *= (ac97_div & 0xfff); + + return rate; +} + +/* * Return the current HSIO bus clock frequency */ static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk) @@ -156,6 +175,12 @@ static const struct clkops clk_pxa3xx_hsio_ops = { .getrate = clk_pxa3xx_hsio_getrate, }; +static const struct clkops clk_pxa3xx_ac97_ops = { + .enable = clk_pxa3xx_cken_enable, + .disable = clk_pxa3xx_cken_disable, + .getrate = clk_pxa3xx_ac97_getrate, +}; + static void clk_pout_enable(struct clk *clk) { OSCC |= OSCC_PEN; @@ -197,8 +222,9 @@ static struct clk pxa3xx_clks[] = { .delay = 70, }, - PXA3xx_CK("LCDCLK", LCD, &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev), - PXA3xx_CK("CAMCLK", CAMERA, &clk_pxa3xx_hsio_ops, NULL), + PXA3xx_CK("LCDCLK", LCD, &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev), + PXA3xx_CK("CAMCLK", CAMERA, &clk_pxa3xx_hsio_ops, NULL), + PXA3xx_CK("AC97CLK", AC97, &clk_pxa3xx_ac97_ops, NULL), PXA3xx_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev), PXA3xx_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev), |