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| author | Thomas Gleixner <tglx@linutronix.de> | 2011-02-22 20:24:26 +0300 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2011-02-22 20:41:48 +0300 |
| commit | 695884fb8acd9857e0e7120ccb2150e30f4b8fef (patch) | |
| tree | 49aa424c1a021ce432e9fa5ea29d37a23e4e30cc /arch/arm/mach-omap2/pm.h | |
| parent | 5df91509d324d44cfb11e55d9cb02fe18b53b045 (diff) | |
| parent | 04bea68b2f0eeebb089ecc67b618795925268b4a (diff) | |
| download | linux-695884fb8acd9857e0e7120ccb2150e30f4b8fef.tar.xz | |
Merge branch 'devicetree/for-x86' of git://git.secretlab.ca/git/linux-2.6 into x86/platform
Reason: x86 devicetree support for ce4100 depends on those device tree
changes scheduled for .39.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/arm/mach-omap2/pm.h')
| -rw-r--r-- | arch/arm/mach-omap2/pm.h | 59 |
1 files changed, 56 insertions, 3 deletions
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h index 0d75bfd1fdbe..1c1b0ab5b978 100644 --- a/arch/arm/mach-omap2/pm.h +++ b/arch/arm/mach-omap2/pm.h @@ -11,7 +11,9 @@ #ifndef __ARCH_ARM_MACH_OMAP2_PM_H #define __ARCH_ARM_MACH_OMAP2_PM_H -#include <plat/powerdomain.h> +#include <linux/err.h> + +#include "powerdomain.h" extern void *omap3_secure_ram_storage; extern void omap3_pm_off_mode_enable(int); @@ -20,6 +22,20 @@ extern int omap3_can_sleep(void); extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state); extern int omap3_idle_init(void); +#if defined(CONFIG_PM_OPP) +extern int omap3_opp_init(void); +extern int omap4_opp_init(void); +#else +static inline int omap3_opp_init(void) +{ + return -EINVAL; +} +static inline int omap4_opp_init(void) +{ + return -EINVAL; +} +#endif + struct cpuidle_params { u8 valid; u32 sleep_latency; @@ -58,7 +74,7 @@ extern u32 sleep_while_idle; #endif #if defined(CONFIG_CPU_IDLE) -extern void omap3_cpuidle_update_states(void); +extern void omap3_cpuidle_update_states(u32, u32); #endif #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) @@ -80,9 +96,46 @@ extern void save_secure_ram_context(u32 *addr); extern void omap3_save_scratchpad_contents(void); extern unsigned int omap24xx_idle_loop_suspend_sz; -extern unsigned int omap34xx_suspend_sz; extern unsigned int save_secure_ram_context_sz; extern unsigned int omap24xx_cpu_suspend_sz; extern unsigned int omap34xx_cpu_suspend_sz; +#define PM_RTA_ERRATUM_i608 (1 << 0) +#define PM_SDRC_WAKEUP_ERRATUM_i583 (1 << 1) + +#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) +extern u16 pm34xx_errata; +#define IS_PM34XX_ERRATUM(id) (pm34xx_errata & (id)) +extern void enable_omap3630_toggle_l2_on_restore(void); +#else +#define IS_PM34XX_ERRATUM(id) 0 +static inline void enable_omap3630_toggle_l2_on_restore(void) { } +#endif /* defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) */ + +#ifdef CONFIG_OMAP_SMARTREFLEX +extern int omap_devinit_smartreflex(void); +extern void omap_enable_smartreflex_on_init(void); +#else +static inline int omap_devinit_smartreflex(void) +{ + return -EINVAL; +} + +static inline void omap_enable_smartreflex_on_init(void) {} +#endif + +#ifdef CONFIG_TWL4030_CORE +extern int omap3_twl_init(void); +extern int omap4_twl_init(void); +#else +static inline int omap3_twl_init(void) +{ + return -EINVAL; +} +static inline int omap4_twl_init(void) +{ + return -EINVAL; +} +#endif + #endif |