diff options
| author | Rajendra Nayak <rnayak@ti.com> | 2013-05-27 14:16:44 +0400 |
|---|---|---|
| committer | Nishanth Menon <nm@ti.com> | 2014-09-08 20:38:43 +0400 |
| commit | 6099dd37c66931085557363b4716483f97cf92a0 (patch) | |
| tree | a8d887251abfc3a3ed4803ba907936985d62a540 /arch/arm/mach-omap2/omap-mpuss-lowpower.c | |
| parent | e97c4eb342055b24da886b56377dc0093e835b4a (diff) | |
| download | linux-6099dd37c66931085557363b4716483f97cf92a0.tar.xz | |
ARM: OMAP5 / DRA7: Enable CPU RET on suspend
On OMAP5 / DRA7, prevent a CPU powerdomain OFF and resulting MPU OSWR
and instead attempt a CPU RET and side effect, MPU RET in suspend.
NOTE: the hardware was originally designed to be capable of achieving
deep power states such as OFF and OSWR, however due to various issues
and risks, deepest valid state was determined to be CSWR - hence we use
the errata framework to handle this case.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[nm@ti.com: updates]
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Diffstat (limited to 'arch/arm/mach-omap2/omap-mpuss-lowpower.c')
| -rw-r--r-- | arch/arm/mach-omap2/omap-mpuss-lowpower.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c index 207fce2d6932..297352f214df 100644 --- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c +++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c @@ -242,6 +242,10 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state) save_state = 1; break; case PWRDM_POWER_RET: + if (IS_PM44XX_ERRATUM(PM_OMAP4_CPU_OSWR_DISABLE)) { + save_state = 0; + break; + } default: /* * CPUx CSWR is invalid hardware state. Also CPUx OSWR |