diff options
| author | Santosh Shilimkar <santosh.shilimkar@ti.com> | 2009-12-12 03:16:35 +0300 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2009-12-12 03:16:35 +0300 |
| commit | 942e2c9e529a57ce2bb1cf984d58f88d9b6e77e5 (patch) | |
| tree | 2892251635eafe9fa4a323a698d501c7ce9cb178 /arch/arm/mach-omap2/omap-headsmp.S | |
| parent | a7c3ae2cb6d144bdf6c582898d2368f5f91a1775 (diff) | |
| download | linux-942e2c9e529a57ce2bb1cf984d58f88d9b6e77e5.tar.xz | |
OMAP4: AuxCoreBoot registers only accessible in secure mode
The AuxCoreBoot0 and AuxCoreBoot1 can be only accessed in secure
mode. Replace the current code with secure monitor API's to access/modify
these registers.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/mach-omap2/omap-headsmp.S')
| -rw-r--r-- | arch/arm/mach-omap2/omap-headsmp.S | 35 |
1 files changed, 27 insertions, 8 deletions
diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S index 4afadba09477..aa3f65c2ac97 100644 --- a/arch/arm/mach-omap2/omap-headsmp.S +++ b/arch/arm/mach-omap2/omap-headsmp.S @@ -27,20 +27,39 @@ * OMAP4 specific entry point for secondary CPU to jump from ROM * code. This routine also provides a holding flag into which * secondary core is held until we're ready for it to initialise. - * The primary core will update the this flag using a hardware - * register AuxCoreBoot1. + * The primary core will update this flag using a hardware + * register AuxCoreBoot0. */ ENTRY(omap_secondary_startup) - mrc p15, 0, r0, c0, c0, 5 - and r0, r0, #0x0f -hold: ldr r1, =OMAP4_AUX_CORE_BOOT1_PA @ read from AuxCoreBoot1 - ldr r2, [r1] - cmp r2, r0 +hold: ldr r12,=0x103 + dsb + smc @ read from AuxCoreBoot0 + mov r0, r0, lsr #9 + mrc p15, 0, r4, c0, c0, 5 + and r4, r4, #0x0f + cmp r0, r4 bne hold /* - * we've been released from the cpu_release,secondary_stack + * we've been released from the wait loop,secondary_stack * should now contain the SVC stack for this core */ b secondary_startup +END(omap_secondary_startup) + +ENTRY(omap_modify_auxcoreboot0) + stmfd sp!, {r1-r12, lr} + ldr r12, =0x104 + dsb + smc + ldmfd sp!, {r1-r12, pc} +END(omap_modify_auxcoreboot0) + +ENTRY(omap_auxcoreboot_addr) + stmfd sp!, {r2-r12, lr} + ldr r12, =0x105 + dsb + smc + ldmfd sp!, {r2-r12, pc} +END(omap_auxcoreboot_addr) |