diff options
| author | Tero Kristo <t-kristo@ti.com> | 2014-12-12 16:22:00 +0300 |
|---|---|---|
| committer | Michael Turquette <mturquette@linaro.org> | 2014-12-16 04:05:08 +0300 |
| commit | 6f8e853d18a98ee95832ffebfaa288d42ae28cd5 (patch) | |
| tree | 9e14134150bd97479885f4731ca076f40044b36f /arch/arm/mach-omap2/dpll44xx.c | |
| parent | b1924c2ec1db98278100010ef87b54406d5ce612 (diff) | |
| download | linux-6f8e853d18a98ee95832ffebfaa288d42ae28cd5.tar.xz | |
ARM: OMAP2+: clock: fix DPLL code to use new determine rate APIs
While the change for determine_rate clock operation was merged,
the OMAP counterpart using these calls was overlooked for some reason,
and caused boot failures on at least OMAP4 platforms. Fixed by updating
the DPLL API calls to use the new parameters.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Fixes: 646cafc6aa ("clk: Change clk_ops->determine_rate")
Cc: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Paul Walmsley <paul@pwsan.com>
Tested-by: Kevin Hilman <khilman@linaro.org>
Reported-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
Diffstat (limited to 'arch/arm/mach-omap2/dpll44xx.c')
| -rw-r--r-- | arch/arm/mach-omap2/dpll44xx.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c index 535822fcf4bb..0e58e5a85d53 100644 --- a/arch/arm/mach-omap2/dpll44xx.c +++ b/arch/arm/mach-omap2/dpll44xx.c @@ -223,7 +223,7 @@ out: */ long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, unsigned long rate, unsigned long *best_parent_rate, - struct clk **best_parent_clk) + struct clk_hw **best_parent_clk) { struct clk_hw_omap *clk = to_clk_hw_omap(hw); struct dpll_data *dd; @@ -237,11 +237,11 @@ long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, unsigned long rate, if (__clk_get_rate(dd->clk_bypass) == rate && (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) { - *best_parent_clk = dd->clk_bypass; + *best_parent_clk = __clk_get_hw(dd->clk_bypass); } else { rate = omap4_dpll_regm4xen_round_rate(hw, rate, best_parent_rate); - *best_parent_clk = dd->clk_ref; + *best_parent_clk = __clk_get_hw(dd->clk_ref); } *best_parent_rate = rate; |