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authorThomas Petazzoni <thomas.petazzoni@free-electrons.com>2012-09-11 16:27:20 +0400
committerJason Cooper <jason@lakedaemon.net>2012-09-21 22:03:44 +0400
commit383b99610e6084878930d4e4682dfc5e9141b038 (patch)
tree1a35c3cac8cbb8335ec6dcb632db4ccd7a21dc68 /arch/arm/mach-mv78xx0/pcie.c
parent060f3d191b1d80312d7c90de2f3c3356db413f40 (diff)
downloadlinux-383b99610e6084878930d4e4682dfc5e9141b038.tar.xz
arm: mach-mv78xx0: use IOMEM() for base address definitions
We now define all virtual base address constants using IOMEM() so that those are naturally typed as void __iomem pointers, and we do the necessary adjustements in the mach-mv78xx0 code. Note that we introduce a few temporary additional "unsigned long" casts when calling into plat-orion functions. Those are removed by followup patches converting plat-orion functions to void __iomem pointers as well. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Tested-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Diffstat (limited to 'arch/arm/mach-mv78xx0/pcie.c')
-rw-r--r--arch/arm/mach-mv78xx0/pcie.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c
index 2e56e86b6d68..e2940fbbcd68 100644
--- a/arch/arm/mach-mv78xx0/pcie.c
+++ b/arch/arm/mach-mv78xx0/pcie.c
@@ -36,8 +36,8 @@ static struct resource pcie_mem_space;
void __init mv78xx0_pcie_id(u32 *dev, u32 *rev)
{
- *dev = orion_pcie_dev_id((void __iomem *)PCIE00_VIRT_BASE);
- *rev = orion_pcie_rev((void __iomem *)PCIE00_VIRT_BASE);
+ *dev = orion_pcie_dev_id(PCIE00_VIRT_BASE);
+ *rev = orion_pcie_rev(PCIE00_VIRT_BASE);
}
static void __init mv78xx0_pcie_preinit(void)
@@ -267,11 +267,11 @@ static struct hw_pci mv78xx0_pci __initdata = {
.map_irq = mv78xx0_pcie_map_irq,
};
-static void __init add_pcie_port(int maj, int min, unsigned long base)
+static void __init add_pcie_port(int maj, int min, void __iomem *base)
{
printk(KERN_INFO "MV78xx0 PCIe port %d.%d: ", maj, min);
- if (orion_pcie_link_up((void __iomem *)base)) {
+ if (orion_pcie_link_up(base)) {
struct pcie_port *pp = &pcie_port[num_pcie_ports++];
printk("link up\n");
@@ -279,7 +279,7 @@ static void __init add_pcie_port(int maj, int min, unsigned long base)
pp->maj = maj;
pp->min = min;
pp->root_bus_nr = -1;
- pp->base = (void __iomem *)base;
+ pp->base = base;
spin_lock_init(&pp->conf_lock);
memset(pp->res, 0, sizeof(pp->res));
} else {
@@ -293,7 +293,7 @@ void __init mv78xx0_pcie_init(int init_port0, int init_port1)
if (init_port0) {
add_pcie_port(0, 0, PCIE00_VIRT_BASE);
- if (!orion_pcie_x4_mode((void __iomem *)PCIE00_VIRT_BASE)) {
+ if (!orion_pcie_x4_mode(PCIE00_VIRT_BASE)) {
add_pcie_port(0, 1, PCIE01_VIRT_BASE);
add_pcie_port(0, 2, PCIE02_VIRT_BASE);
add_pcie_port(0, 3, PCIE03_VIRT_BASE);