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| author | Jonathan Austin <jonathan.austin@arm.com> | 2016-08-30 19:27:19 +0300 |
|---|---|---|
| committer | Russell King <rmk+kernel@armlinux.org.uk> | 2016-09-06 17:51:07 +0300 |
| commit | f5a5c89e36d0897b65e4e6bc2f646f75f8074263 (patch) | |
| tree | beaaf4b52d04056a54fea8fc7d9706f2d01f481b /arch/arm/kernel | |
| parent | 296909ee6d9cf98f68a61d5e9774ff5435df2c6a (diff) | |
| download | linux-f5a5c89e36d0897b65e4e6bc2f646f75f8074263.tar.xz | |
ARM: 8604/1: V7M: Add support for reading the CTR with read_cpuid_cachetype()
With the addition of caches to the V7M Architecture a new Cache Type
Register (CTR) is defined at 0xE000ED7C. This register serves the same
purpose as the V7A/R version and accessed via the read_cpuid_cachetype.
Signed-off-by: Jonathan Austin <jonathan.austin@arm.com>
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Tested-by: Andras Szemzo <sza@esh.hu>
Tested-by: Joachim Eastwood <manabian@gmail.com>
Tested-by: Alexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/kernel')
| -rw-r--r-- | arch/arm/kernel/setup.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index d7568808eb7b..34e3f3c45634 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -312,11 +312,12 @@ static void __init cacheid_init(void) { unsigned int arch = cpu_architecture(); - if (arch == CPU_ARCH_ARMv7M) { - cacheid = 0; - } else if (arch >= CPU_ARCH_ARMv6) { + if (arch >= CPU_ARCH_ARMv6) { unsigned int cachetype = read_cpuid_cachetype(); - if ((cachetype & (7 << 29)) == 4 << 29) { + + if ((arch == CPU_ARCH_ARMv7M) && !cachetype) { + cacheid = 0; + } else if ((cachetype & (7 << 29)) == 4 << 29) { /* ARMv7 register format */ arch = CPU_ARCH_ARMv7; cacheid = CACHEID_VIPT_NONALIASING; |