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| author | Will Deacon <will.deacon@arm.com> | 2011-06-03 20:40:15 +0400 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2011-07-07 22:20:53 +0400 |
| commit | 0c205cbe20654616e2f8389c0c1ff707d9dccb63 (patch) | |
| tree | bff2cc25f48b911faac970f5c0b98b6a795509e9 /arch/arm/kernel/perf_event.c | |
| parent | 6d4eaf991c654af54a19c0fa48e0ad62cefbc37c (diff) | |
| download | linux-0c205cbe20654616e2f8389c0c1ff707d9dccb63.tar.xz | |
ARM: perf: add support for the Cortex-A5 PMU
This patch adds support for the Cortex-A5 PMU to the ARMv7 perf-event
backend.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm/kernel/perf_event.c')
| -rw-r--r-- | arch/arm/kernel/perf_event.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c index d53c0abc4dd3..df4e517687bf 100644 --- a/arch/arm/kernel/perf_event.c +++ b/arch/arm/kernel/perf_event.c @@ -660,6 +660,9 @@ init_hw_perf_events(void) case 0xC090: /* Cortex-A9 */ armpmu = armv7_a9_pmu_init(); break; + case 0xC050: /* Cortex-A5 */ + armpmu = armv7_a5_pmu_init(); + break; } /* Intel CPUs [xscale]. */ } else if (0x69 == implementor) { |