diff options
| author | Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> | 2014-05-20 18:48:10 +0400 |
|---|---|---|
| committer | Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> | 2014-10-29 21:44:45 +0300 |
| commit | 652538c4d27df714efc4dd092e6defe87c0bbeb9 (patch) | |
| tree | 5bd705cec6173dcf85cc22435747a4dea1c55252 /arch/arm/boot | |
| parent | 60daa9f71de148cbfc33187c2ce6d3dd80cf8fa0 (diff) | |
| download | linux-652538c4d27df714efc4dd092e6defe87c0bbeb9.tar.xz | |
ARM: dts: berlin: Add SDHCI controller nodes to BG2/BG2CD
Marvell Berlin BG2 has three, BG2CD just one pxav3 compatible
sdhci controllers, add them to the corresponding DT SoC
includes.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Diffstat (limited to 'arch/arm/boot')
| -rw-r--r-- | arch/arm/boot/dts/berlin2.dtsi | 34 | ||||
| -rw-r--r-- | arch/arm/boot/dts/berlin2cd.dtsi | 9 |
2 files changed, 43 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi index bbdad9510f19..20e7c394a008 100644 --- a/arch/arm/boot/dts/berlin2.dtsi +++ b/arch/arm/boot/dts/berlin2.dtsi @@ -53,6 +53,35 @@ ranges = <0 0xf7000000 0x1000000>; + sdhci0: sdhci@ab0000 { + compatible = "mrvl,pxav3-mmc"; + reg = <0xab0000 0x200>; + clocks = <&chip CLKID_SDIO0XIN>, <&chip CLKID_SDIO0>; + clock-names = "io", "core"; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + sdhci1: sdhci@ab0800 { + compatible = "mrvl,pxav3-mmc"; + reg = <0xab0800 0x200>; + clocks = <&chip CLKID_SDIO1XIN>, <&chip CLKID_SDIO1>; + clock-names = "io", "core"; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + sdhci2: sdhci@ab1000 { + compatible = "mrvl,pxav3-mmc"; + reg = <0xab1000 0x200>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&chip CLKID_NFC_ECC>, <&chip CLKID_NFC>; + clock-names = "io", "core"; + pinctrl-0 = <&emmc_pmux>; + pinctrl-names = "default"; + status = "disabled"; + }; + l2: l2-cache-controller@ac0000 { compatible = "marvell,tauros3-cache", "arm,pl310-cache"; reg = <0xac0000 0x1000>; @@ -289,6 +318,11 @@ reg = <0xea0000 0x400>; clocks = <&refclk>; clock-names = "refclk"; + + emmc_pmux: emmc-pmux { + groups = "G26"; + function = "emmc"; + }; }; apb@fc0000 { diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berlin2cd.dtsi index fff23aad8205..9e338ff80fd3 100644 --- a/arch/arm/boot/dts/berlin2cd.dtsi +++ b/arch/arm/boot/dts/berlin2cd.dtsi @@ -45,6 +45,15 @@ ranges = <0 0xf7000000 0x1000000>; + sdhci0: sdhci@ab0000 { + compatible = "mrvl,pxav3-mmc"; + reg = <0xab0000 0x200>; + clocks = <&chip CLKID_SDIO0XIN>, <&chip CLKID_SDIO0>; + clock-names = "io", "core"; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + l2: l2-cache-controller@ac0000 { compatible = "arm,pl310-cache"; reg = <0xac0000 0x1000>; |