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authorJoel Stanley <joel@jms.id.au>2020-08-31 03:46:52 +0300
committerJoel Stanley <joel@jms.id.au>2020-08-31 03:46:57 +0300
commit0dd0c8c492fa70707ca4f0d36dcb2e3c64105b16 (patch)
treea420abd8f26264544246602c60d161a7cc4de390 /arch/arm/boot
parent31d8605658d37d9197a989838508481d5dc1d8bc (diff)
parent9ece50d8a470ca7235ffd6ac0f9c5f0f201fe2c8 (diff)
downloadlinux-dev-5.8.tar.xz
Merge tag 'v5.8.5' into dev-5.8dev-5.8
This is the 5.8.5 stable release Signed-off-by: Joel Stanley <joel@jms.id.au>
Diffstat (limited to 'arch/arm/boot')
-rw-r--r--arch/arm/boot/dts/at91-sama5d3_xplained.dts2
-rw-r--r--arch/arm/boot/dts/exynos5422-odroid-core.dtsi6
-rw-r--r--arch/arm/boot/dts/exynos5800.dtsi6
-rw-r--r--arch/arm/boot/dts/r8a7793-gose.dts4
-rw-r--r--arch/arm/boot/dts/stm32mp15-pinctrl.dtsi128
-rw-r--r--arch/arm/boot/dts/sunxi-bananapi-m2-plus-v1.2.dtsi18
6 files changed, 85 insertions, 79 deletions
diff --git a/arch/arm/boot/dts/at91-sama5d3_xplained.dts b/arch/arm/boot/dts/at91-sama5d3_xplained.dts
index 61f068a7b362..7abf555cd2fe 100644
--- a/arch/arm/boot/dts/at91-sama5d3_xplained.dts
+++ b/arch/arm/boot/dts/at91-sama5d3_xplained.dts
@@ -128,7 +128,7 @@
};
macb0: ethernet@f0028000 {
- phy-mode = "rgmii";
+ phy-mode = "rgmii-rxid";
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index ab27ff8bc3dc..afe090578e8f 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -411,12 +411,6 @@
status = "okay";
};
-&bus_fsys {
- operating-points-v2 = <&bus_fsys2_opp_table>;
- devfreq = <&bus_wcore>;
- status = "okay";
-};
-
&bus_fsys2 {
operating-points-v2 = <&bus_fsys2_opp_table>;
devfreq = <&bus_wcore>;
diff --git a/arch/arm/boot/dts/exynos5800.dtsi b/arch/arm/boot/dts/exynos5800.dtsi
index dfb99ab53c3e..526729dad53f 100644
--- a/arch/arm/boot/dts/exynos5800.dtsi
+++ b/arch/arm/boot/dts/exynos5800.dtsi
@@ -23,17 +23,17 @@
&cluster_a15_opp_table {
opp-2000000000 {
opp-hz = /bits/ 64 <2000000000>;
- opp-microvolt = <1312500>;
+ opp-microvolt = <1312500 1312500 1500000>;
clock-latency-ns = <140000>;
};
opp-1900000000 {
opp-hz = /bits/ 64 <1900000000>;
- opp-microvolt = <1262500>;
+ opp-microvolt = <1262500 1262500 1500000>;
clock-latency-ns = <140000>;
};
opp-1800000000 {
opp-hz = /bits/ 64 <1800000000>;
- opp-microvolt = <1237500>;
+ opp-microvolt = <1237500 1237500 1500000>;
clock-latency-ns = <140000>;
};
opp-1700000000 {
diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts
index 79baf06019f5..10c3536b8e3d 100644
--- a/arch/arm/boot/dts/r8a7793-gose.dts
+++ b/arch/arm/boot/dts/r8a7793-gose.dts
@@ -336,7 +336,7 @@
reg = <0x20>;
remote = <&vin1>;
- port {
+ ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -394,7 +394,7 @@
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
default-input = <0>;
- port {
+ ports {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
index 7eb858732d6d..cc505458da2f 100644
--- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
@@ -1574,143 +1574,157 @@
};
};
- usart2_pins_a: usart2-0 {
+ uart4_pins_a: uart4-0 {
pins1 {
- pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */
- <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
+ pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
- pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */
- <STM32_PINMUX('D', 3, AF7)>; /* USART2_CTS_NSS */
+ pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
bias-disable;
};
};
- usart2_sleep_pins_a: usart2-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('F', 5, ANALOG)>, /* USART2_TX */
- <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */
- <STM32_PINMUX('D', 6, ANALOG)>, /* USART2_RX */
- <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */
- };
- };
-
- usart2_pins_b: usart2-1 {
+ uart4_pins_b: uart4-1 {
pins1 {
- pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */
- <STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */
+ pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
- pinmux = <STM32_PINMUX('F', 4, AF7)>, /* USART2_RX */
- <STM32_PINMUX('E', 15, AF7)>; /* USART2_CTS_NSS */
+ pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
bias-disable;
};
};
- usart2_sleep_pins_b: usart2-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('F', 5, ANALOG)>, /* USART2_TX */
- <STM32_PINMUX('A', 1, ANALOG)>, /* USART2_RTS */
- <STM32_PINMUX('F', 4, ANALOG)>, /* USART2_RX */
- <STM32_PINMUX('E', 15, ANALOG)>; /* USART2_CTS_NSS */
+ uart4_pins_c: uart4-2 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
+ bias-disable;
};
};
- usart3_pins_a: usart3-0 {
+ uart7_pins_a: uart7-0 {
pins1 {
- pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */
+ pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
- pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
+ pinmux = <STM32_PINMUX('E', 7, AF7)>, /* UART7_RX */
+ <STM32_PINMUX('E', 10, AF7)>, /* UART7_CTS */
+ <STM32_PINMUX('E', 9, AF7)>; /* UART7_RTS */
bias-disable;
};
};
- uart4_pins_a: uart4-0 {
+ uart7_pins_b: uart7-1 {
pins1 {
- pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
+ pinmux = <STM32_PINMUX('F', 7, AF7)>; /* UART7_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
- pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
+ pinmux = <STM32_PINMUX('F', 6, AF7)>; /* UART7_RX */
bias-disable;
};
};
- uart4_pins_b: uart4-1 {
+ uart8_pins_a: uart8-0 {
pins1 {
- pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */
+ pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
- pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
+ pinmux = <STM32_PINMUX('E', 0, AF8)>; /* UART8_RX */
bias-disable;
};
};
- uart4_pins_c: uart4-2 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
+ spi4_pins_a: spi4-0 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 12, AF5)>, /* SPI4_SCK */
+ <STM32_PINMUX('E', 6, AF5)>; /* SPI4_MOSI */
bias-disable;
drive-push-pull;
- slew-rate = <0>;
+ slew-rate = <1>;
};
pins2 {
- pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
+ pinmux = <STM32_PINMUX('E', 13, AF5)>; /* SPI4_MISO */
bias-disable;
};
};
- uart7_pins_a: uart7-0 {
+ usart2_pins_a: usart2-0 {
pins1 {
- pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART4_TX */
+ pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */
+ <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
- pinmux = <STM32_PINMUX('E', 7, AF7)>, /* UART4_RX */
- <STM32_PINMUX('E', 10, AF7)>, /* UART4_CTS */
- <STM32_PINMUX('E', 9, AF7)>; /* UART4_RTS */
+ pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */
+ <STM32_PINMUX('D', 3, AF7)>; /* USART2_CTS_NSS */
bias-disable;
};
};
- uart7_pins_b: uart7-1 {
+ usart2_sleep_pins_a: usart2-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 5, ANALOG)>, /* USART2_TX */
+ <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */
+ <STM32_PINMUX('D', 6, ANALOG)>, /* USART2_RX */
+ <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */
+ };
+ };
+
+ usart2_pins_b: usart2-1 {
pins1 {
- pinmux = <STM32_PINMUX('F', 7, AF7)>; /* UART7_TX */
+ pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */
+ <STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
- pinmux = <STM32_PINMUX('F', 6, AF7)>; /* UART7_RX */
+ pinmux = <STM32_PINMUX('F', 4, AF7)>, /* USART2_RX */
+ <STM32_PINMUX('E', 15, AF7)>; /* USART2_CTS_NSS */
bias-disable;
};
};
- uart8_pins_a: uart8-0 {
+ usart2_sleep_pins_b: usart2-sleep-1 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 5, ANALOG)>, /* USART2_TX */
+ <STM32_PINMUX('A', 1, ANALOG)>, /* USART2_RTS */
+ <STM32_PINMUX('F', 4, ANALOG)>, /* USART2_RX */
+ <STM32_PINMUX('E', 15, ANALOG)>; /* USART2_CTS_NSS */
+ };
+ };
+
+ usart3_pins_a: usart3-0 {
pins1 {
- pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */
+ pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
- pinmux = <STM32_PINMUX('E', 0, AF8)>; /* UART8_RX */
+ pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
bias-disable;
};
};
@@ -1776,18 +1790,4 @@
bias-disable;
};
};
-
- spi4_pins_a: spi4-0 {
- pins {
- pinmux = <STM32_PINMUX('E', 12, AF5)>, /* SPI4_SCK */
- <STM32_PINMUX('E', 6, AF5)>; /* SPI4_MOSI */
- bias-disable;
- drive-push-pull;
- slew-rate = <1>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('E', 13, AF5)>; /* SPI4_MISO */
- bias-disable;
- };
- };
};
diff --git a/arch/arm/boot/dts/sunxi-bananapi-m2-plus-v1.2.dtsi b/arch/arm/boot/dts/sunxi-bananapi-m2-plus-v1.2.dtsi
index 22466afd38a3..235994a4a2eb 100644
--- a/arch/arm/boot/dts/sunxi-bananapi-m2-plus-v1.2.dtsi
+++ b/arch/arm/boot/dts/sunxi-bananapi-m2-plus-v1.2.dtsi
@@ -16,15 +16,27 @@
regulator-type = "voltage";
regulator-boot-on;
regulator-always-on;
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1300000>;
+ regulator-min-microvolt = <1108475>;
+ regulator-max-microvolt = <1308475>;
regulator-ramp-delay = <50>; /* 4ms */
gpios = <&r_pio 0 1 GPIO_ACTIVE_HIGH>; /* PL1 */
gpios-states = <0x1>;
- states = <1100000 0>, <1300000 1>;
+ states = <1108475 0>, <1308475 1>;
};
};
&cpu0 {
cpu-supply = <&reg_vdd_cpux>;
};
+
+&cpu1 {
+ cpu-supply = <&reg_vdd_cpux>;
+};
+
+&cpu2 {
+ cpu-supply = <&reg_vdd_cpux>;
+};
+
+&cpu3 {
+ cpu-supply = <&reg_vdd_cpux>;
+};
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-17 23:37:15 +0300