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authorBiju Das <biju.das@bp.renesas.com>2018-11-27 14:56:34 +0300
committerSimon Horman <horms+renesas@verge.net.au>2018-12-04 17:34:39 +0300
commit54234e80858cf3730917d71af80a13ac4b8f26dc (patch)
tree1c484195de137170dc033156c7019d6b6d6012a9 /arch/arm/boot/dts/r8a7744.dtsi
parent491e70588805a8895bff6ac5a626c8bb481fea1c (diff)
downloadlinux-54234e80858cf3730917d71af80a13ac4b8f26dc.tar.xz
ARM: dts: r8a7744: Add xhci support
Add a device node for the xhci controller on the Renesas RZ/G1N (r8a7744) SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r8a7744.dtsi')
-rw-r--r--arch/arm/boot/dts/r8a7744.dtsi20
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 992d622b5393..33e15c5f21c9 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -1424,6 +1424,26 @@
dma-channels = <13>;
};
+ /*
+ * pci1 and xhci share the same phy, therefore only one of them
+ * can be active at any one time. If both of them are enabled,
+ * a race condition will determine who'll control the phy.
+ * A firmware file is needed by the xhci driver in order for
+ * USB 3.0 to work properly.
+ */
+ xhci: usb@ee000000 {
+ compatible = "renesas,xhci-r8a7744",
+ "renesas,rcar-gen2-xhci";
+ reg = <0 0xee000000 0 0xc00>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 328>;
+ power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+ resets = <&cpg 328>;
+ phys = <&usb2 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
pci0: pci@ee090000 {
compatible = "renesas,pci-r8a7744",
"renesas,pci-rcar-gen2";