diff options
| author | Matthew McClintock <mmcclint@codeaurora.org> | 2016-03-24 01:05:07 +0300 |
|---|---|---|
| committer | Andy Gross <andy.gross@linaro.org> | 2016-04-20 05:42:16 +0300 |
| commit | 13ad4fd36a815f1f4fb96c7308ea104bafc6bdb9 (patch) | |
| tree | 37074b01fc93056e2723f76b6a06c2031554de27 /arch/arm/boot/dts/qcom-ipq4019.dtsi | |
| parent | 8196dd5e5c4c3b623a23e25060588a7129f0574e (diff) | |
| download | linux-13ad4fd36a815f1f4fb96c7308ea104bafc6bdb9.tar.xz | |
qcom: ipq4019: add spi node to ipq4019 SoC and DK01 device tree
This will allow boards to enable the SPI bus
Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/qcom-ipq4019.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/qcom-ipq4019.dtsi | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index acb851d55a19..99e64f4881bc 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -15,12 +15,18 @@ #include "skeleton.dtsi" #include <dt-bindings/clock/qcom,gcc-ipq4019.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> / { model = "Qualcomm Technologies, Inc. IPQ4019"; compatible = "qcom,ipq4019"; interrupt-parent = <&intc>; + aliases { + spi0 = &spi_0; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -108,6 +114,18 @@ interrupts = <0 208 0>; }; + spi_0: spi@78b5000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x78b5000 0x600>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + acc0: clock-controller@b088000 { compatible = "qcom,kpss-acc-v1"; reg = <0x0b088000 0x1000>, <0xb008000 0x1000>; |