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authorVladimir Zapolskiy <vz@mleia.com>2016-04-27 00:10:31 +0300
committerVladimir Zapolskiy <vz@mleia.com>2016-04-28 00:39:00 +0300
commitd9a95d57647bc93f41f13a4ec6eafc1ebef7b533 (patch)
treee389d10615595e07eb84649b6b3233de60e8c988 /arch/arm/boot/dts/lpc3250-ea3250.dts
parent118e24cd626b8857b94eefec6f1108fef4017e51 (diff)
downloadlinux-d9a95d57647bc93f41f13a4ec6eafc1ebef7b533.tar.xz
ARM: dts: lpc32xx: ea3250: add SoC name prefix to board dts file
To simplify matching of DTS files of all NXP LPC32xx powered boards by a file name add 'lpc3250' prefix to Embedded Artists LPC3250 board dts file. Acked-by: Sylvain Lemieux <slemieux.tyco@gmail.com> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Diffstat (limited to 'arch/arm/boot/dts/lpc3250-ea3250.dts')
-rw-r--r--arch/arm/boot/dts/lpc3250-ea3250.dts272
1 files changed, 272 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/lpc3250-ea3250.dts b/arch/arm/boot/dts/lpc3250-ea3250.dts
new file mode 100644
index 000000000000..52b3ed10283a
--- /dev/null
+++ b/arch/arm/boot/dts/lpc3250-ea3250.dts
@@ -0,0 +1,272 @@
+/*
+ * Embedded Artists LPC3250 board
+ *
+ * Copyright 2012 Roland Stigge <stigge@antcom.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+#include "lpc32xx.dtsi"
+
+/ {
+ model = "Embedded Artists LPC3250 board based on NXP LPC3250";
+ compatible = "ea,ea3250", "nxp,lpc3250";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x4000000>;
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ autorepeat;
+ button@21 {
+ label = "Interrupt Key";
+ linux,code = <103>;
+ gpios = <&gpio 4 1 0>; /* GPI_P3 1 */
+ };
+ key1 {
+ label = "KEY1";
+ linux,code = <1>;
+ gpios = <&pca9532 0 0>;
+ };
+ key2 {
+ label = "KEY2";
+ linux,code = <2>;
+ gpios = <&pca9532 1 0>;
+ };
+ key3 {
+ label = "KEY3";
+ linux,code = <3>;
+ gpios = <&pca9532 2 0>;
+ };
+ key4 {
+ label = "KEY4";
+ linux,code = <4>;
+ gpios = <&pca9532 3 0>;
+ };
+ joy0 {
+ label = "Joystick Key 0";
+ linux,code = <10>;
+ gpios = <&gpio 2 0 0>; /* P2.0 */
+ };
+ joy1 {
+ label = "Joystick Key 1";
+ linux,code = <11>;
+ gpios = <&gpio 2 1 0>; /* P2.1 */
+ };
+ joy2 {
+ label = "Joystick Key 2";
+ linux,code = <12>;
+ gpios = <&gpio 2 2 0>; /* P2.2 */
+ };
+ joy3 {
+ label = "Joystick Key 3";
+ linux,code = <13>;
+ gpios = <&gpio 2 3 0>; /* P2.3 */
+ };
+ joy4 {
+ label = "Joystick Key 4";
+ linux,code = <14>;
+ gpios = <&gpio 2 4 0>; /* P2.4 */
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ /* LEDs on OEM Board */
+
+ led1 {
+ gpios = <&gpio 5 14 1>; /* GPO_P3 14, GPIO 93, active low */
+ linux,default-trigger = "timer";
+ default-state = "off";
+ };
+
+ led2 {
+ gpios = <&gpio 2 10 1>; /* P2.10, active low */
+ default-state = "off";
+ };
+
+ led3 {
+ gpios = <&gpio 2 11 1>; /* P2.11, active low */
+ default-state = "off";
+ };
+
+ led4 {
+ gpios = <&gpio 2 12 1>; /* P2.12, active low */
+ default-state = "off";
+ };
+
+ /* LEDs on Base Board */
+
+ lede1 {
+ gpios = <&pca9532 8 0>;
+ default-state = "off";
+ };
+ lede2 {
+ gpios = <&pca9532 9 0>;
+ default-state = "off";
+ };
+ lede3 {
+ gpios = <&pca9532 10 0>;
+ default-state = "off";
+ };
+ lede4 {
+ gpios = <&pca9532 11 0>;
+ default-state = "off";
+ };
+ lede5 {
+ gpios = <&pca9532 12 0>;
+ default-state = "off";
+ };
+ lede6 {
+ gpios = <&pca9532 13 0>;
+ default-state = "off";
+ };
+ lede7 {
+ gpios = <&pca9532 14 0>;
+ default-state = "off";
+ };
+ lede8 {
+ gpios = <&pca9532 15 0>;
+ default-state = "off";
+ };
+ };
+};
+
+/* 3-axis accelerometer X,Y,Z (or AD-IN instead of Z) */
+&adc {
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+
+ uda1380: uda1380@18 {
+ compatible = "nxp,uda1380";
+ reg = <0x18>;
+ power-gpio = <&gpio 0x59 0>;
+ reset-gpio = <&gpio 0x51 0>;
+ dac-clk = "wspll";
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c256";
+ reg = <0x50>;
+ };
+
+ eeprom@57 {
+ compatible = "atmel,24c64";
+ reg = <0x57>;
+ };
+
+ pca9532: pca9532@60 {
+ compatible = "nxp,pca9532";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x60>;
+ };
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+};
+
+&i2cusb {
+ clock-frequency = <100000>;
+
+ isp1301: usb-transceiver@2d {
+ compatible = "nxp,isp1301";
+ reg = <0x2d>;
+ };
+};
+
+&mac {
+ phy-mode = "rmii";
+ use-iram;
+};
+
+/* Here, choose exactly one from: ohci, usbd */
+&ohci /* &usbd */ {
+ transceiver = <&isp1301>;
+ status = "okay";
+};
+
+&sd {
+ wp-gpios = <&pca9532 5 0>;
+ cd-gpios = <&pca9532 4 0>;
+ cd-inverted;
+ bus-width = <4>;
+ status = "okay";
+};
+
+/* 128MB Flash via SLC NAND controller */
+&slc {
+ status = "okay";
+
+ nxp,wdr-clks = <14>;
+ nxp,wwidth = <260000000>;
+ nxp,whold = <104000000>;
+ nxp,wsetup = <200000000>;
+ nxp,rdr-clks = <14>;
+ nxp,rwidth = <34666666>;
+ nxp,rhold = <104000000>;
+ nxp,rsetup = <200000000>;
+ nand-on-flash-bbt;
+ gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ mtd0@00000000 {
+ label = "ea3250-boot";
+ reg = <0x00000000 0x00080000>;
+ read-only;
+ };
+
+ mtd1@00080000 {
+ label = "ea3250-uboot";
+ reg = <0x00080000 0x000c0000>;
+ read-only;
+ };
+
+ mtd2@00140000 {
+ label = "ea3250-kernel";
+ reg = <0x00140000 0x00400000>;
+ };
+
+ mtd3@00540000 {
+ label = "ea3250-rootfs";
+ reg = <0x00540000 0x07ac0000>;
+ };
+ };
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&uart6 {
+ status = "okay";
+};