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authorDave Gerlach <d-gerlach@ti.com>2016-05-19 02:36:32 +0300
committerTony Lindgren <tony@atomide.com>2016-06-10 14:58:07 +0300
commitb82ffb337b69947bf82d936827fe5c6e2ad6abdd (patch)
treef206608ae8dd0544e5d3547ca8b4036422de1551 /arch/arm/boot/dts/dra7.dtsi
parent62e4feed0b0b9bc73d0aa843a6a6d259cb5197e4 (diff)
downloadlinux-b82ffb337b69947bf82d936827fe5c6e2ad6abdd.tar.xz
ARM: dts: dra7: Move cpus node to parent dts for dra74x and dra72x
Nearly all of the information in the cpus node, especially for cpu0, is the same between dra74x and dra72x so move the common information to the parent dra7.dtsi to avoid duplication of data. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/boot/dts/dra7.dtsi')
-rw-r--r--arch/arm/boot/dts/dra7.dtsi27
1 files changed, 27 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index cc4cb76431f6..b1e9f5c0fb79 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -73,6 +73,33 @@
interrupt-parent = <&gic>;
};
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0>;
+
+ operating-points = <
+ /* kHz uV */
+ 1000000 1060000
+ 1176000 1160000
+ >;
+
+ clocks = <&dpll_mpu_ck>;
+ clock-names = "cpu";
+
+ clock-latency = <300000>; /* From omap-cpufreq driver */
+
+ /* cooling options */
+ cooling-min-level = <0>;
+ cooling-max-level = <2>;
+ #cooling-cells = <2>; /* min followed by max */
+ };
+ };
+
/*
* The soc node represents the soc top level view. It is used for IPs
* that are not memory mapped in the MPU view or for the MPU itself.