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| author | Maor Gottlieb <maorg@nvidia.com> | 2021-06-06 11:23:41 +0300 |
|---|---|---|
| committer | Saeed Mahameed <saeedm@nvidia.com> | 2021-06-10 03:20:04 +0300 |
| commit | 4aaf96ac8b45d8e2e019b6b53cce65a73c4ace2c (patch) | |
| tree | 478e718d0fbb1bee9e229246140d669b711ef967 /README | |
| parent | c189716b2a7c1d2d8658e269735273caa1c38b54 (diff) | |
| download | linux-4aaf96ac8b45d8e2e019b6b53cce65a73c4ace2c.tar.xz | |
net/mlx5: DR, Don't use SW steering when RoCE is not supported
SW steering uses RC QP to write/read to/from ICM, hence it's not
supported when RoCE is not supported as well.
Fixes: 70605ea545e8 ("net/mlx5: DR, Expose APIs for direct rule managing")
Signed-off-by: Maor Gottlieb <maorg@nvidia.com>
Reviewed-by: Alex Vesker <valex@nvidia.com>
Reviewed-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
Diffstat (limited to 'README')
0 files changed, 0 insertions, 0 deletions