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| author | Julien Grall <julien.grall@arm.com> | 2018-08-14 13:33:32 +0300 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2018-08-29 13:33:19 +0300 |
| commit | afce0cc9ad8aa510650e781a51e43c26e2a34cf6 (patch) | |
| tree | 748e88295b151f0e46d08e9b9c35168e222de9e6 /Documentation | |
| parent | 5b394b2ddf0347bef56e50c69a58773c94343ff3 (diff) | |
| download | linux-afce0cc9ad8aa510650e781a51e43c26e2a34cf6.tar.xz | |
Documentation/arm64/sve: Couple of improvements and typos
- Fix mismatch between SVE registers (Z) and FPSIMD register (V)
- Don't prefix the path for [3] with Linux to stay consistent with
[1] and [2].
Signed-off-by: Julien Grall <julien.grall@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/arm64/sve.txt | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/Documentation/arm64/sve.txt b/Documentation/arm64/sve.txt index f128f736b4a5..7169a0ec41d8 100644 --- a/Documentation/arm64/sve.txt +++ b/Documentation/arm64/sve.txt @@ -200,7 +200,7 @@ prctl(PR_SVE_SET_VL, unsigned long arg) thread. * Changing the vector length causes all of P0..P15, FFR and all bits of - Z0..V31 except for Z0 bits [127:0] .. Z31 bits [127:0] to become + Z0..Z31 except for Z0 bits [127:0] .. Z31 bits [127:0] to become unspecified. Calling PR_SVE_SET_VL with vl equal to the thread's current vector length, or calling PR_SVE_SET_VL with the PR_SVE_SET_VL_ONEXEC flag, does not constitute a change to the vector length for this purpose. @@ -500,7 +500,7 @@ References [2] arch/arm64/include/uapi/asm/ptrace.h AArch64 Linux ptrace ABI definitions -[3] linux/Documentation/arm64/cpu-feature-registers.txt +[3] Documentation/arm64/cpu-feature-registers.txt [4] ARM IHI0055C http://infocenter.arm.com/help/topic/com.arm.doc.ihi0055c/IHI0055C_beta_aapcs64.pdf |