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authorSerge Semin <Sergey.Semin@baikalelectronics.ru>2020-12-10 12:09:42 +0300
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2021-01-12 14:41:32 +0300
commit1fd7b103451e7662712a315faf8e5f41e0e8bb00 (patch)
treea833a0a6eaa6939d3b20a04763149a95071ee802 /Documentation/devicetree
parente9cd063547a115acd6ca8ad436748c16d8d98821 (diff)
downloadlinux-1fd7b103451e7662712a315faf8e5f41e0e8bb00.tar.xz
dt-bindings: usb: qcom,dwc3: Validate DWC3 sub-node
Qualcomm msm8996/sc7180/sdm845 DWC3 compatible DT nodes are supposed to have a DWC USB3 compatible sub-node to describe a fully functioning USB interface. Let's use the available DWC USB3 DT schema to validate the Qualcomm DWC3 sub-nodes. Note since the generic DWC USB3 DT node is supposed to be named as generic USB HCD ("^usb(@.*)?") one we have to accordingly fix the sub-nodes name regexp and fix the DT node example. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Link: https://lore.kernel.org/r/20201210090944.16283-19-Sergey.Semin@baikalelectronics.ru Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'Documentation/devicetree')
-rw-r--r--Documentation/devicetree/bindings/usb/qcom,dwc3.yaml9
1 files changed, 3 insertions, 6 deletions
diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
index 2cf525d21e05..b336662e838c 100644
--- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
+++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
@@ -103,11 +103,8 @@ properties:
# Required child node:
patternProperties:
- "^dwc3@[0-9a-f]+$":
- type: object
- description:
- A child node must exist to represent the core DWC3 IP block
- The content of the node is defined in dwc3.txt.
+ "^usb@[0-9a-f]+$":
+ $ref: snps,dwc3.yaml#
required:
- compatible
@@ -162,7 +159,7 @@ examples:
resets = <&gcc GCC_USB30_PRIM_BCR>;
- dwc3@a600000 {
+ usb@a600000 {
compatible = "snps,dwc3";
reg = <0 0x0a600000 0 0xcd00>;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;