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authorHeiko Stuebner <heiko@sntech.de>2019-10-24 01:38:50 +0300
committerKishon Vijay Abraham I <kishon@ti.com>2019-10-31 14:24:01 +0300
commit3817c79611792333a33f6548a2aaf701a70fc593 (patch)
treef715a2ffab52d04d1f7785d1f8e756f8ad7d4931 /Documentation/devicetree/bindings/phy
parentb7535a3bc0bac70e9644fb35cdeffabb59f578ee (diff)
downloadlinux-3817c79611792333a33f6548a2aaf701a70fc593.tar.xz
dt-bindings: phy: add yaml binding for rockchip,px30-dsi-dphy
This adds a yaml binding for the external dsi phy found on Rockchip socs of the px30, rk3128 and rk3368 variants. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Diffstat (limited to 'Documentation/devicetree/bindings/phy')
-rw-r--r--Documentation/devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml75
1 files changed, 75 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml b/Documentation/devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml
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index 000000000000..bb0da87bcd84
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+++ b/Documentation/devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip MIPI DPHY with additional LVDS/TTL modes
+
+maintainers:
+ - Heiko Stuebner <heiko@sntech.de>
+
+properties:
+ "#phy-cells":
+ const: 0
+
+ "#clock-cells":
+ const: 0
+
+ compatible:
+ enum:
+ - rockchip,px30-dsi-dphy
+ - rockchip,rk3128-dsi-dphy
+ - rockchip,rk3368-dsi-dphy
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: PLL reference clock
+ - description: Module clock
+
+ clock-names:
+ items:
+ - const: ref
+ - const: pclk
+
+ power-domains:
+ maxItems: 1
+ description: phandle to the associated power domain
+
+ resets:
+ items:
+ - description: exclusive PHY reset line
+
+ reset-names:
+ items:
+ - const: apb
+
+required:
+ - "#phy-cells"
+ - "#clock-cells"
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+
+additionalProperties: false
+
+examples:
+ - |
+ dsi_dphy: phy@ff2e0000 {
+ compatible = "rockchip,px30-video-phy";
+ reg = <0x0 0xff2e0000 0x0 0x10000>;
+ clocks = <&pmucru 13>, <&cru 12>;
+ clock-names = "ref", "pclk";
+ #clock-cells = <0>;
+ resets = <&cru 12>;
+ reset-names = "apb";
+ #phy-cells = <0>;
+ };
+
+...