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| author | Thierry Reding <thierry.reding@avionic-design.de> | 2012-04-13 17:08:08 +0400 |
|---|---|---|
| committer | Joerg Roedel <joerg.roedel@amd.com> | 2012-04-16 15:57:16 +0400 |
| commit | 7cffae421e3cd29410ef4d75f2244655fdde3b60 (patch) | |
| tree | 7d618d7d3600bb21de11aa976ec5795188f563a5 /Documentation/devicetree/bindings/iommu | |
| parent | 543f3f33b6165585f755858baaa95530513f5c1e (diff) | |
| download | linux-7cffae421e3cd29410ef4d75f2244655fdde3b60.tar.xz | |
iommu: tegra/gart: Add device tree support
This commit adds device tree support for the GART hardware available on
NVIDIA Tegra 20 SoCs.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
Diffstat (limited to 'Documentation/devicetree/bindings/iommu')
| -rw-r--r-- | Documentation/devicetree/bindings/iommu/nvidia,tegra20-gart.txt | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/iommu/nvidia,tegra20-gart.txt b/Documentation/devicetree/bindings/iommu/nvidia,tegra20-gart.txt new file mode 100644 index 000000000000..2d87b9191fce --- /dev/null +++ b/Documentation/devicetree/bindings/iommu/nvidia,tegra20-gart.txt @@ -0,0 +1,14 @@ +NVIDIA Tegra 20 GART + +Required properties: +- compatible: "nvidia,tegra20-gart" +- reg: Two pairs of cells specifying the physical address and size of + the memory controller registers and the GART aperture respectively. + +Example: + + gart: gart@7000f000 { + compatible = "nvidia,tegra20-gart"; + reg = < 0x7000f000 0x00000100 /* controller registers */ + 0x58000000 0x02000000 >; /* GART aperture */ + }; |