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author | Yuantian Tang <andy.tang@nxp.com> | 2017-11-22 04:40:53 +0300 |
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committer | Stephen Boyd <sboyd@codeaurora.org> | 2017-12-22 02:57:28 +0300 |
commit | 36ab04671570fcd0e33868eba83f361d76c36bbf (patch) | |
tree | 545b657ecd4c004d8f3e1d63e4b1d76b696a7c2b /Documentation/devicetree/bindings/clock | |
parent | 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323 (diff) | |
download | linux-36ab04671570fcd0e33868eba83f361d76c36bbf.tar.xz |
clk: qoriq: add more divider clocks support
More divider clocks are needed by IP. So enlarge the PLL divider
array to accommodate more divider clocks.
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'Documentation/devicetree/bindings/clock')
-rw-r--r-- | Documentation/devicetree/bindings/clock/qoriq-clock.txt | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt index 6498e1fdbb33..97f46adac85f 100644 --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt @@ -78,6 +78,7 @@ second cell is the clock index for the specified type. 2 hwaccel index (n in CLKCGnHWACSR) 3 fman 0 for fm1, 1 for fm2 4 platform pll 0=pll, 1=pll/2, 2=pll/3, 3=pll/4 + 4=pll/5, 5=pll/6, 6=pll/7, 7=pll/8 5 coreclk must be 0 3. Example |