clk: ti: Add support for FAPLL on dm816x

On dm816x the clocks are sourced from a FAPLL (Flying Adder PLL)
that does not seem to be used on the other omap variants.

There are four instances of the FAPLL on dm816x that each have three
to seven child synthesizers.

I've set up the FAPLL as a single fapll.c driver. Later on we could
potentially have the PLL code generic. To do that, we would have to
consider the following:

1. Setting the PLL to bypass mode also sets the child synthesizers
   into bypass mode. As the bypass rate can also be generated by
   the PLL in regular mode, there's no way for the child synthesizers
   to detect the bypass mode based on the parent clock rate.

2. The PLL registers control the power for each of the child
   syntheriser.

Note that the clocks are currently still missing the set_rate
implementation so things are still running based on the bootloader
values. That's OK for now as most of the outputs have dividers and
those can be set using the existing TI component clock code.

I have verified that the extclk rates are correct for a few clocks,
so adding the set_rate support should be fairly trivial later on.

This code is partially based on the TI81XX-LINUX-PSP-04.04.00.02
patches published at:

http://downloads.ti.com/dsps/dsps_public_sw/psp/LinuxPSP/TI81XX_04_04/04_04_00_02/index_FDS.html

Cc: Brian Hutchinson <b.hutchman@gmail.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>

1 files changed, 33 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/clock/ti/fapll.txt b/Documentation/devicetree/bindings/clock/ti/fapll.txt
new file mode 100644
index 000000000000..c19b3f253b8c
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/fapll.txt
@@ -0,0 +1,33 @@
+Binding for Texas Instruments FAPLL clock.
+
+Binding status: Unstable - ABI compatibility may be broken in the future
+
+This binding uses the common clock binding[1]. It assumes a
+register-mapped FAPLL with usually two selectable input clocks
+(reference clock and bypass clock), and one or more child
+syntesizers.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be "ti,dm816-fapll-clock"
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : link phandles of parent clocks (clk-ref and clk-bypass)
+- reg : address and length of the register set for controlling the FAPLL.
+
+Examples:
+	main_fapll: main_fapll {
+		#clock-cells = <1>;
+		compatible = "ti,dm816-fapll-clock";
+		reg = <0x400 0x40>;
+		clocks = <&sys_clkin_ck &sys_clkin_ck>;
+		clock-indices = <1>, <2>, <3>, <4>, <5>,
+				<6>, <7>;
+		clock-output-names = "main_pll_clk1",
+				     "main_pll_clk2",
+				     "main_pll_clk3",
+				     "main_pll_clk4",
+				     "main_pll_clk5",
+				     "main_pll_clk6",
+				     "main_pll_clk7";
+	};