diff options
| author | Will Deacon <will.deacon@arm.com> | 2015-06-29 15:59:01 +0300 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2015-07-31 17:01:14 +0300 |
| commit | b6c084d7aa8bca21920cbbe13ad58572fa85ece6 (patch) | |
| tree | 5dfcdb11b45a7e62cb9d36810304973240c23b73 /Documentation/devicetree/bindings/arm/pmu.txt | |
| parent | 8ae81c25cfe962a788a28e023d9a78934d807f7d (diff) | |
| download | linux-b6c084d7aa8bca21920cbbe13ad58572fa85ece6.tar.xz | |
ARM: perf: extend interrupt-affinity property for PPIs
On systems containing multiple, heterogeneous clusters we need a way to
associate a PMU "device" with the CPU(s) on which it exists. For PMUs
that signal overflow with SPIs, this relationship is determined via the
"interrupt-affinity" property, which contains a list of phandles to CPU
nodes for the PMU. For PMUs using PPIs, the per-cpu nature of the
interrupt isn't enough to determine the set of CPUs which actually
contain the device.
This patch allows the interrupt-affinity property to be specified on a
PMU node irrespective of the interrupt type. For PPIs, it identifies
the set of CPUs signalling the PPI in question.
Tested-by: Stephen Boyd <sboyd@codeaurora.org> # Krait PMU
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'Documentation/devicetree/bindings/arm/pmu.txt')
| -rw-r--r-- | Documentation/devicetree/bindings/arm/pmu.txt | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/arm/pmu.txt b/Documentation/devicetree/bindings/arm/pmu.txt index 3b5f5d1088c6..435251fa9ce0 100644 --- a/Documentation/devicetree/bindings/arm/pmu.txt +++ b/Documentation/devicetree/bindings/arm/pmu.txt @@ -26,13 +26,19 @@ Required properties: Optional properties: -- interrupt-affinity : Valid only when using SPIs, specifies a list of phandles - to CPU nodes corresponding directly to the affinity of +- interrupt-affinity : When using SPIs, specifies a list of phandles to CPU + nodes corresponding directly to the affinity of the SPIs listed in the interrupts property. - This property should be present when there is more than + When using a PPI, specifies a list of phandles to CPU + nodes corresponding to the set of CPUs which have + a PMU of this type signalling the PPI listed in the + interrupts property. + + This property should be present when there is more than a single SPI. + - qcom,no-pc-write : Indicates that this PMU doesn't support the 0xc and 0xd events. |