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| author | Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> | 2020-06-24 15:34:06 +0300 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2020-06-24 16:25:06 +0300 |
| commit | f4617be35b4b547e82d30993f56d631dfc2d5f88 (patch) | |
| tree | d92c35cf9b547e06fe6750234389762d930549a7 | |
| parent | 2d21889f8b5c50f65f5162bc972b0b1626b97be2 (diff) | |
| download | linux-f4617be35b4b547e82d30993f56d631dfc2d5f88.tar.xz | |
arm64: kpti: Add KRYO{3, 4}XX silver CPU cores to kpti safelist
QCOM KRYO{3,4}XX silver/LITTLE CPU cores are based on Cortex-A55
and are meltdown safe, hence add them to kpti_safe_list[].
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Link: https://lore.kernel.org/r/20200624123406.3472-1-saiprakash.ranjan@codeaurora.org
Signed-off-by: Will Deacon <will@kernel.org>
| -rw-r--r-- | arch/arm64/kernel/cpufeature.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 4ae41670c2e6..9f63053a63a9 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -1290,6 +1290,8 @@ static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), + MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER), + MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER), { /* sentinel */ } }; char const *str = "kpti command line option"; |