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| author | Arnd Bergmann <arnd@arndb.de> | 2016-07-21 15:40:28 +0300 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2016-07-21 15:40:28 +0300 |
| commit | d95eabc7b8ee4c8ef471e8a97aa62d353b110880 (patch) | |
| tree | 9db74153231272a68a5a9f27a367dbfc4a18b755 | |
| parent | 1b2d8b94c8781adfb1eeb9cd1cbe23fab601519a (diff) | |
| parent | e0c3f92a08f3e0a95024d0d032564fdc1ee96f54 (diff) | |
| download | linux-d95eabc7b8ee4c8ef471e8a97aa62d353b110880.tar.xz | |
Merge tag 'renesas-dt-fixes-for-v4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt
Merge "Renesas ARM Based SoC DT Fixes for v4.8" from Simon Horman:
* Corrections to r8a7792
* tag 'renesas-dt-fixes-for-v4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: dts: r8a7792: remove ADSP clock
ARM: dts: r8a7792: add PLL1 divided by 2 clock
| -rw-r--r-- | arch/arm/boot/dts/r8a7792.dtsi | 9 | ||||
| -rw-r--r-- | include/dt-bindings/clock/r8a7792-clock.h | 1 |
2 files changed, 8 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index 75256ef4a04d..3fd61d7ab906 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -279,11 +279,18 @@ clocks = <&extal_clk>; #clock-cells = <1>; clock-output-names = "main", "pll0", "pll1", "pll3", - "lb", "qspi", "z", "adsp"; + "lb", "qspi", "z"; #power-domain-cells = <0>; }; /* Fixed factor clocks */ + pll1_div2_clk: pll1_div2 { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7792_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; zs_clk: zs { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7792_CLK_PLL1>; diff --git a/include/dt-bindings/clock/r8a7792-clock.h b/include/dt-bindings/clock/r8a7792-clock.h index 89a5155913f6..9a8b392ceb00 100644 --- a/include/dt-bindings/clock/r8a7792-clock.h +++ b/include/dt-bindings/clock/r8a7792-clock.h @@ -18,7 +18,6 @@ #define R8A7792_CLK_LB 4 #define R8A7792_CLK_QSPI 5 #define R8A7792_CLK_Z 6 -#define R8A7792_CLK_ADSP 7 /* MSTP0 */ #define R8A7792_CLK_MSIOF0 0 |