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authorAlex Deucher <alexander.deucher@amd.com>2016-08-22 23:31:36 +0300
committerAlex Deucher <alexander.deucher@amd.com>2016-08-24 23:25:02 +0300
commitc4795ca642b8bd76b5b6ffba41ba909543273d43 (patch)
tree89aab658073fea03c5d2ae1c2a5a34d07dca8103
parent1b5836492de6a753f6bb420f500848761c6f84f3 (diff)
downloadlinux-c4795ca642b8bd76b5b6ffba41ba909543273d43.tar.xz
drm/amdgpu: fix IB alignment for UVD
According to the hw team, it should be 16, not 8. Cc: Peter Fang <peter.fang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 4c8e68a82c47..eab8d7313244 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -292,7 +292,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
type = AMD_IP_BLOCK_TYPE_UVD;
ring_mask = adev->uvd.ring.ready ? 1 : 0;
ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
- ib_size_alignment = 8;
+ ib_size_alignment = 16;
break;
case AMDGPU_HW_IP_VCE:
type = AMD_IP_BLOCK_TYPE_VCE;