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| author | Andre Przywara <andre.przywara@arm.com> | 2019-11-21 04:18:33 +0300 |
|---|---|---|
| committer | Maxime Ripard <maxime@cerno.tech> | 2019-12-10 12:43:34 +0300 |
| commit | 7aa9b9eb7d6a8fde7acbe0446444f7e3fae1fe3b (patch) | |
| tree | 0af556ee0cd4d4ce46ceb02d082a85b248eb2625 | |
| parent | fe67dfcb44c6477dbde6c897c7787bf20e2281a3 (diff) | |
| download | linux-7aa9b9eb7d6a8fde7acbe0446444f7e3fae1fe3b.tar.xz | |
arm64: dts: allwinner: H6: Add PMU mode
Add the Performance Monitoring Unit (PMU) device tree node to the H6
.dtsi, which tells DT users which interrupts are triggered by PMU
overflow events on each core. The numbers come from the manual and have
been checked in U-Boot and with perf in Linux.
Tested with perf record and taskset on a Pine H64.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
| -rw-r--r-- | arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index 29824081b43b..24ffe2dcbddb 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -70,6 +70,16 @@ clock-output-names = "ext_osc32k"; }; + pmu { + compatible = "arm,cortex-a53-pmu", + "arm,armv8-pmuv3"; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + psci { compatible = "arm,psci-0.2"; method = "smc"; |