diff options
author | Arnd Bergmann <arnd@arndb.de> | 2020-05-21 23:41:59 +0300 |
---|---|---|
committer | Arnd Bergmann <arnd@arndb.de> | 2020-05-21 23:42:00 +0300 |
commit | 622a380d621fa79c962cac6ac1a0518ca5a07a1c (patch) | |
tree | 3e772add8c57160d5bb9de2141c1cceac88cafbe | |
parent | 409b62942019333a1a435cc9e6a9f20282e38459 (diff) | |
parent | f0e5405b9ebf084c34c41f5d38a0013bee166f4d (diff) | |
download | linux-622a380d621fa79c962cac6ac1a0518ca5a07a1c.tar.xz |
Merge tag 'v5.7-next-dts64' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/dt
MT2712:
- replace deprecated compatible for the usb PHY
MT6797:
- switch to SPDX identifier
- add and enable I2C device for x20 development board
- add I2C compatible to the binding description
MT7622:
- add Wi-Fi device and enable it for the Bananpi-R64
MT8173:
- add CPU capacities based on Dhryston benchmark
- fix DT build warnings
- set throtteling range to limitless
- add Elm and Hana devices on which several chromebooks are based
- add Global Command Queue entries to the users
MT8183:
- split cpuidle states in two as the clusters have different target residencies
* tag 'v5.7-next-dts64' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
arm64: dts: mt8173: Add capacity-dmips-mhz attributes
arm64: dts: mt2712: use non-empty ranges for usb-phy
arm64: dts: mt8173: fix mdp aliases property name
arm64: dts: mediatek: Switch to SPDX license identifier for MT6797 SoC
arm64: dts: mediatek: Enable I2C support for 96Boards X20 Development board
arm64: dts: mediatek: Add I2C support for MT6797 SoC
dt-bindings: i2c: Document I2C controller binding for MT6797 SoC
arm64: dts: mt8173: fix cooling device range
arm64: dts: mediatek: add mt8173 elm and hana board
arm64: dts: mt8173: fix unit name warnings
arm64: dts: mt8173: add uart aliases
dt-bindings: arm64: dts: mediatek: Add mt8173 elm and hana
arm64: dts: mt8183: adjust cpuidle target residency
arm64: dts: mt8173: Add gce setting in mmsys and display node
arm64: dts: mt7622: add built-in Wi-Fi device nodes
Link: https://lore.kernel.org/r/2794a8db-c14f-ac34-9e28-9f3700db6c4c@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
-rw-r--r-- | Documentation/devicetree/bindings/arm/mediatek.yaml | 22 | ||||
-rw-r--r-- | Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt | 1 | ||||
-rw-r--r-- | arch/arm64/boot/dts/mediatek/Makefile | 3 | ||||
-rw-r--r-- | arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 42 | ||||
-rw-r--r-- | arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts | 49 | ||||
-rw-r--r-- | arch/arm64/boot/dts/mediatek/mt6797.dtsi | 229 | ||||
-rw-r--r-- | arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts | 4 | ||||
-rw-r--r-- | arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 4 | ||||
-rw-r--r-- | arch/arm64/boot/dts/mediatek/mt7622.dtsi | 11 | ||||
-rw-r--r-- | arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts | 27 | ||||
-rw-r--r-- | arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dts | 14 | ||||
-rw-r--r-- | arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtsi | 70 | ||||
-rw-r--r-- | arch/arm64/boot/dts/mediatek/mt8173-elm.dts | 14 | ||||
-rw-r--r-- | arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi | 1173 | ||||
-rw-r--r-- | arch/arm64/boot/dts/mediatek/mt8173.dtsi | 78 | ||||
-rw-r--r-- | arch/arm64/boot/dts/mediatek/mt8183.dtsi | 26 |
16 files changed, 1705 insertions, 62 deletions
diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 4043c5046441..abc544dde692 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -84,6 +84,28 @@ properties: - enum: - mediatek,mt8135-evbp1 - const: mediatek,mt8135 + - description: Google Elm (Acer Chromebook R13) + items: + - const: google,elm-rev8 + - const: google,elm-rev7 + - const: google,elm-rev6 + - const: google,elm-rev5 + - const: google,elm-rev4 + - const: google,elm-rev3 + - const: google,elm + - const: mediatek,mt8173 + - description: Google Hana (Lenovo Chromebook N23 Yoga, C330, 300e,...) + items: + - const: google,hana-rev6 + - const: google,hana-rev5 + - const: google,hana-rev4 + - const: google,hana-rev3 + - const: google,hana + - const: mediatek,mt8173 + - description: Google Hana rev7 (Poin2 Chromebook 11C) + items: + - const: google,hana-rev7 + - const: mediatek,mt8173 - items: - enum: - mediatek,mt8173-evb diff --git a/Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt b/Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt index 68f6d73a8b73..88b71c1b32c9 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt @@ -8,6 +8,7 @@ Required properties: "mediatek,mt2712-i2c": for MediaTek MT2712 "mediatek,mt6577-i2c": for MediaTek MT6577 "mediatek,mt6589-i2c": for MediaTek MT6589 + "mediatek,mt6797-i2c", "mediatek,mt6577-i2c": for MediaTek MT6797 "mediatek,mt7622-i2c": for MediaTek MT7622 "mediatek,mt7623-i2c", "mediatek,mt6577-i2c": for MediaTek MT7623 "mediatek,mt7629-i2c", "mediatek,mt2712-i2c": for MediaTek MT7629 diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 2f8967cb8717..a57af9da9f5c 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -6,6 +6,9 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana-rev7.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi index 2cd8b33886e5..f29ade61931d 100644 --- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi @@ -703,30 +703,31 @@ }; u3phy0: usb-phy@11290000 { - compatible = "mediatek,mt2712-u3phy"; - #address-cells = <2>; - #size-cells = <2>; - ranges; + compatible = "mediatek,mt2712-tphy", + "mediatek,generic-tphy-v2"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11290000 0x9000>; status = "okay"; - u2port0: usb-phy@11290000 { - reg = <0 0x11290000 0 0x700>; + u2port0: usb-phy@0 { + reg = <0x0 0x700>; clocks = <&clk26m>; clock-names = "ref"; #phy-cells = <1>; status = "okay"; }; - u2port1: usb-phy@11298000 { - reg = <0 0x11298000 0 0x700>; + u2port1: usb-phy@8000 { + reg = <0x8000 0x700>; clocks = <&clk26m>; clock-names = "ref"; #phy-cells = <1>; status = "okay"; }; - u3port0: usb-phy@11298700 { - reg = <0 0x11298700 0 0x900>; + u3port0: usb-phy@8700 { + reg = <0x8700 0x900>; clocks = <&clk26m>; clock-names = "ref"; #phy-cells = <1>; @@ -766,30 +767,31 @@ }; u3phy1: usb-phy@112e0000 { - compatible = "mediatek,mt2712-u3phy"; - #address-cells = <2>; - #size-cells = <2>; - ranges; + compatible = "mediatek,mt2712-tphy", + "mediatek,generic-tphy-v2"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x112e0000 0x9000>; status = "okay"; - u2port2: usb-phy@112e0000 { - reg = <0 0x112e0000 0 0x700>; + u2port2: usb-phy@0 { + reg = <0x0 0x700>; clocks = <&clk26m>; clock-names = "ref"; #phy-cells = <1>; status = "okay"; }; - u2port3: usb-phy@112e8000 { - reg = <0 0x112e8000 0 0x700>; + u2port3: usb-phy@8000 { + reg = <0x8000 0x700>; clocks = <&clk26m>; clock-names = "ref"; #phy-cells = <1>; status = "okay"; }; - u3port1: usb-phy@112e8700 { - reg = <0 0x112e8700 0 0x900>; + u3port1: usb-phy@8700 { + reg = <0x8700 0x900>; clocks = <&clk26m>; clock-names = "ref"; #phy-cells = <1>; diff --git a/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts b/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts index 13939d55b85b..eff9e8dbd076 100644 --- a/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts +++ b/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts @@ -28,6 +28,55 @@ }; }; +/* HDMI */ +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; +}; + +/* HS - I2C2 */ +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + status = "okay"; +}; + +/* HS - I2C3 */ +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins_a>; + status = "okay"; +}; + +/* LS - I2C0 */ +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins_a>; + status = "okay"; +}; + +/* LS - I2C1 */ +&i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_pins_a>; + status = "okay"; +}; + +/* POWER_VPROC */ +&i2c6 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_pins_a>; + status = "okay"; +}; + +/* FAN53555 */ +&i2c7 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_pins_a>; + status = "okay"; +}; + &uart1 { status = "okay"; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/mediatek/mt6797.dtsi b/arch/arm64/boot/dts/mediatek/mt6797.dtsi index 136ef9527a0d..9fa2214b353e 100644 --- a/arch/arm64/boot/dts/mediatek/mt6797.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6797.dtsi @@ -1,14 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2017 MediaTek Inc. * Author: Mars.C <mars.cheng@mediatek.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include <dt-bindings/clock/mt6797-clk.h> @@ -155,6 +148,62 @@ <MT6797_GPIO233__FUNC_UTXD1>; }; }; + + i2c0_pins_a: i2c0 { + pins0 { + pinmux = <MT6797_GPIO37__FUNC_SCL0_0>, + <MT6797_GPIO38__FUNC_SDA0_0>; + }; + }; + + i2c1_pins_a: i2c1 { + pins1 { + pinmux = <MT6797_GPIO55__FUNC_SCL1_0>, + <MT6797_GPIO56__FUNC_SDA1_0>; + }; + }; + + i2c2_pins_a: i2c2 { + pins2 { + pinmux = <MT6797_GPIO96__FUNC_SCL2_0>, + <MT6797_GPIO95__FUNC_SDA2_0>; + }; + }; + + i2c3_pins_a: i2c3 { + pins3 { + pinmux = <MT6797_GPIO75__FUNC_SDA3_0>, + <MT6797_GPIO74__FUNC_SCL3_0>; + }; + }; + + i2c4_pins_a: i2c4 { + pins4 { + pinmux = <MT6797_GPIO238__FUNC_SDA4_0>, + <MT6797_GPIO239__FUNC_SCL4_0>; + }; + }; + + i2c5_pins_a: i2c5 { + pins5 { + pinmux = <MT6797_GPIO240__FUNC_SDA5_0>, + <MT6797_GPIO241__FUNC_SCL5_0>; + }; + }; + + i2c6_pins_a: i2c6 { + pins6 { + pinmux = <MT6797_GPIO152__FUNC_SDA6_0>, + <MT6797_GPIO151__FUNC_SCL6_0>; + }; + }; + + i2c7_pins_a: i2c7 { + pins7 { + pinmux = <MT6797_GPIO154__FUNC_SDA7_0>, + <MT6797_GPIO153__FUNC_SCL7_0>; + }; + }; }; scpsys: power-controller@10006000 { @@ -233,6 +282,170 @@ status = "disabled"; }; + i2c0: i2c@11007000 { + compatible = "mediatek,mt6797-i2c", + "mediatek,mt6577-i2c"; + id = <0>; + reg = <0 0x11007000 0 0x1000>, + <0 0x11000100 0 0x80>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infrasys CLK_INFRA_I2C0>, + <&infrasys CLK_INFRA_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <10>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@11008000 { + compatible = "mediatek,mt6797-i2c", + "mediatek,mt6577-i2c"; + id = <1>; + reg = <0 0x11008000 0 0x1000>, + <0 0x11000180 0 0x80>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infrasys CLK_INFRA_I2C1>, + <&infrasys CLK_INFRA_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <10>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c8: i2c@11009000 { + compatible = "mediatek,mt6797-i2c", + "mediatek,mt6577-i2c"; + id = <8>; + reg = <0 0x11009000 0 0x1000>, + <0 0x11000200 0 0x80>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infrasys CLK_INFRA_I2C2>, + <&infrasys CLK_INFRA_AP_DMA>, + <&infrasys CLK_INFRA_I2C2_ARB>; + clock-names = "main", "dma", "arb"; + clock-div = <10>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c9: i2c@1100d000 { + compatible = "mediatek,mt6797-i2c", + "mediatek,mt6577-i2c"; + id = <9>; + reg = <0 0x1100d000 0 0x1000>, + <0 0x11000280 0 0x80>; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infrasys CLK_INFRA_I2C3>, + <&infrasys CLK_INFRA_AP_DMA>, + <&infrasys CLK_INFRA_I2C3_ARB>; + clock-names = "main", "dma", "arb"; + clock-div = <10>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c6: i2c@1100e000 { + compatible = "mediatek,mt6797-i2c", + "mediatek,mt6577-i2c"; + id = <6>; + reg = <0 0x1100e000 0 0x1000>, + <0 0x11000500 0 0x80>; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infrasys CLK_INFRA_I2C_APPM>, + <&infrasys CLK_INFRA_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <10>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c7: i2c@11010000 { + compatible = "mediatek,mt6797-i2c", + "mediatek,mt6577-i2c"; + id = <7>; + reg = <0 0x11010000 0 0x1000>, + <0 0x11000580 0 0x80>; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infrasys CLK_INFRA_I2C_GPUPM>, + <&infrasys CLK_INFRA_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <10>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@11011000 { + compatible = "mediatek,mt6797-i2c", + "mediatek,mt6577-i2c"; + id = <4>; + reg = <0 0x11011000 0 0x1000>, + <0 0x11000300 0 0x80>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infrasys CLK_INFRA_I2C4>, + <&infrasys CLK_INFRA_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <10>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@11013000 { + compatible = "mediatek,mt6797-i2c", + "mediatek,mt6577-i2c"; + id = <2>; + reg = <0 0x11013000 0 0x1000>, + <0 0x11000400 0 0x80>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infrasys CLK_INFRA_I2C2_IMM>, + <&infrasys CLK_INFRA_AP_DMA>, + <&infrasys CLK_INFRA_I2C2_ARB>; + clock-names = "main", "dma", "arb"; + clock-div = <10>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@11014000 { + compatible = "mediatek,mt6797-i2c", + "mediatek,mt6577-i2c"; + id = <3>; + reg = <0 0x11014000 0 0x1000>, + <0 0x11000480 0 0x80>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infrasys CLK_INFRA_I2C3_IMM>, + <&infrasys CLK_INFRA_AP_DMA>, + <&infrasys CLK_INFRA_I2C3_ARB>; + clock-names = "main", "dma", "arb"; + clock-div = <10>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@1101c000 { + compatible = "mediatek,mt6797-i2c", + "mediatek,mt6577-i2c"; + id = <5>; + reg = <0 0x1101c000 0 0x1000>, + <0 0x11000380 0 0x80>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infrasys CLK_INFRA_I2C5>, + <&infrasys CLK_INFRA_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <10>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + mmsys: mmsys_config@14000000 { compatible = "mediatek,mt6797-mmsys", "syscon"; reg = <0 0x14000000 0 0x1000>; diff --git a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts index 83e10591e0e5..d174ad214857 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts @@ -543,3 +543,7 @@ pinctrl-0 = <&watchdog_pins>; status = "okay"; }; + +&wmac { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts index 3f783348c66a..0b4de627f96e 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts @@ -506,3 +506,7 @@ pinctrl-0 = <&watchdog_pins>; status = "okay"; }; + +&wmac { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi index 339dc9f88f43..1a39e0ef776b 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi @@ -699,6 +699,17 @@ status = "disabled"; }; + wmac: wmac@18000000 { + compatible = "mediatek,mt7622-wmac"; + reg = <0 0x18000000 0 0x100000>; + interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_LOW>; + + mediatek,infracfg = <&infracfg>; + status = "disabled"; + + power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>; + }; + ssusbsys: ssusbsys@1a000000 { compatible = "mediatek,mt7622-ssusbsys", "syscon"; diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts new file mode 100644 index 000000000000..44f6149c1307 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2019 MediaTek Inc. + */ + +/dts-v1/; +#include "mt8173-elm-hana.dtsi" + +/ { + model = "Google Hanawl"; + compatible = "google,hana-rev7", "mediatek,mt8173"; +}; + +&cpu_thermal { + trips { + cpu_crit: cpu_crit0 { + temperature = <100000>; + type = "critical"; + }; + }; +}; + +&gpio_keys { + /delete-node/tablet_mode; + /delete-node/volume_down; + /delete-node/volume_up; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dts b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dts new file mode 100644 index 000000000000..c234296755e1 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2016 MediaTek Inc. + */ + +/dts-v1/; +#include "mt8173-elm-hana.dtsi" + +/ { + model = "Google Hana"; + compatible = "google,hana-rev6", "google,hana-rev5", + "google,hana-rev4", "google,hana-rev3", + "google,hana", "mediatek,mt8173"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtsi b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtsi new file mode 100644 index 000000000000..bdcd35cecad9 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtsi @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2016 MediaTek Inc. + */ + +#include "mt8173-elm.dtsi" + +&i2c0 { + clock-frequency = <200000>; +}; + +&i2c3 { + touchscreen2: touchscreen@34 { + compatible = "melfas,mip4_ts"; + reg = <0x34>; + interrupt-parent = <&pio>; + interrupts = <88 IRQ_TYPE_LEVEL_LOW>; + }; + + /* + * Lenovo 100e Chromebook 2nd Gen (MTK) and Lenovo 300e Chromebook 2nd + * Gen (MTK) are using synaptics touchscreen (hid-over-i2c driver) as a + * second source touchscreen. + */ + touchscreen3: touchscreen@20 { + compatible = "hid-over-i2c"; + reg = <0x20>; + hid-descr-addr = <0x0020>; + interrupt-parent = <&pio>; + interrupts = <88 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c4 { + /* + * Lenovo 100e Chromebook 2nd Gen (MTK) and Lenovo 300e Chromebook 2nd + * Gen (MTK) are using synaptics trackpad (hid-over-i2c driver) as a + * second source trackpad. + */ + trackpad2: trackpad@2c { + compatible = "hid-over-i2c"; + interrupt-parent = <&pio>; + interrupts = <117 IRQ_TYPE_LEVEL_LOW>; + reg = <0x2c>; + hid-descr-addr = <0x0020>; + wakeup-source; + }; +}; + +&mmc1 { + wp-gpios = <&pio 42 GPIO_ACTIVE_HIGH>; +}; + +&pio { + hdmi_mux_pins: hdmi_mux_pins { + pins2 { + pinmux = <MT8173_PIN_98_URTS1__FUNC_GPIO98>; + bias-pull-up; + output-high; + }; + }; + + mmc1_pins_default: mmc1default { + pins_wp { + pinmux = <MT8173_PIN_42_DSI_TE__FUNC_GPIO42>; + input-enable; + bias-pull-up; + }; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm.dts b/arch/arm64/boot/dts/mediatek/mt8173-elm.dts new file mode 100644 index 000000000000..e9e4ac0b74b2 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2016 MediaTek Inc. + */ + +/dts-v1/; +#include "mt8173-elm.dtsi" + +/ { + model = "Google Elm"; + compatible = "google,elm-rev8", "google,elm-rev7", "google,elm-rev6", + "google,elm-rev5", "google,elm-rev4", "google,elm-rev3", + "google,elm", "mediatek,mt8173"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi new file mode 100644 index 000000000000..a5a12b2599a4 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi @@ -0,0 +1,1173 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2016 MediaTek Inc. + */ + +#include <dt-bindings/input/input.h> +#include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/gpio/gpio.h> +#include "mt8173.dtsi" + +/ { + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x80000000>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 1000000>; + power-supply = <&bl_fixed_reg>; + enable-gpios = <&pio 95 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&disp_pwm0_pins>; + status = "okay"; + }; + + bl_fixed_reg: fixedregulator2 { + compatible = "regulator-fixed"; + regulator-name = "bl_fixed"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + startup-delay-us = <1000>; + enable-active-high; + gpio = <&pio 32 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bl_fixed_pins>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pins>; + + lid { + label = "Lid"; + gpios = <&pio 69 GPIO_ACTIVE_LOW>; + linux,code = <SW_LID>; + linux,input-type = <EV_SW>; + gpio-key,wakeup; + }; + + power { + label = "Power"; + gpios = <&pio 14 GPIO_ACTIVE_HIGH>; + linux,code = <KEY_POWER>; + debounce-interval = <30>; + gpio-key,wakeup; + }; + + tablet_mode { + label = "Tablet_mode"; + gpios = <&pio 121 GPIO_ACTIVE_HIGH>; + linux,code = <SW_TABLET_MODE>; + linux,input-type = <EV_SW>; + gpio-key,wakeup; + }; + + volume_down { + label = "Volume_down"; + gpios = <&pio 123 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEDOWN>; + }; + + volume_up { + label = "Volume_up"; + gpios = <&pio 124 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + }; + }; + + panel: panel { + compatible = "lg,lp120up1"; + power-supply = <&panel_fixed_3v3>; + ddc-i2c-bus = <&i2c0>; + backlight = <&backlight>; + + port { + panel_in: endpoint { + remote-endpoint = <&ps8640_out>; + }; + }; + }; + + panel_fixed_3v3: regulator1 { + compatible = "regulator-fixed"; + regulator-name = "PANEL_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&pio 41 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_fixed_pins>; + }; + + ps8640_fixed_1v2: regulator2 { + compatible = "regulator-fixed"; + regulator-name = "PS8640_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-enable-ramp-delay = <2000>; + enable-active-high; + regulator-boot-on; + gpio = <&pio 30 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&ps8640_fixed_pins>; + }; + + sdio_fixed_3v3: fixedregulator0 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pio 85 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio_fixed_3v3_pins>; + }; + + sound: sound { + compatible = "mediatek,mt8173-rt5650"; + mediatek,audio-codec = <&rt5650 &hdmi0>; + mediatek,platform = <&afe>; + pinctrl-names = "default"; + pinctrl-0 = <&aud_i2s2>; + + mediatek,mclk = <1>; + codec-capture { + sound-dai = <&rt5650 1>; + }; + }; + + hdmicon: connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + ddc-i2c-bus = <&hdmiddc0>; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi0_out>; + }; + }; + }; +}; + +&cec { + status = "okay"; +}; + +&cpu0 { + proc-supply = <&mt6397_vpca15_reg>; +}; + +&cpu1 { + proc-supply = <&mt6397_vpca15_reg>; +}; + +&cpu2 { + proc-supply = <&da9211_vcpu_reg>; + sram-supply = <&mt6397_vsramca7_reg>; +}; + +&cpu3 { + proc-supply = <&da9211_vcpu_reg>; + sram-supply = <&mt6397_vsramca7_reg>; +}; + +&cpu_thermal { + sustainable-power = <4500>; /* milliwatts */ + trips { + threshold: trip-point0 { + temperature = <60000>; + }; + + target: trip-point1 { + temperature = <65000>; + }; + }; +}; + +&dsi0 { + status = "okay"; + ports { + port { + dsi0_out: endpoint { + remote-endpoint = <&ps8640_in>; + }; + }; + }; +}; + +&dpi0 { + status = "okay"; +}; + +&hdmi0 { + status = "okay"; + ports { + port@1 { + reg = <1>; + + hdmi0_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; +}; + +&hdmi_phy { + status = "okay"; + mediatek,ibias = <0xc>; +}; + +&i2c0 { + status = "okay"; + + rt5650: audio-codec@1a { + compatible = "realtek,rt5650"; + reg = <0x1a>; + avdd-supply = <&mt6397_vgp1_reg>; + cpvdd-supply = <&mt6397_vcama_reg>; + interrupt-parent = <&pio>; + interrupts = <3 IRQ_TYPE_EDGE_BOTH>; + pinctrl-names = "default"; + pinctrl-0 = <&rt5650_irq>; + #sound-dai-cells = <1>; + realtek,dmic1-data-pin = <2>; + realtek,jd-mode = <2>; + }; + + ps8640: edp-bridge@8 { + compatible = "parade,ps8640"; + reg = <0x8>; + powerdown-gpios = <&pio 127 GPIO_ACTIVE_LOW>; + reset-gpios = <&pio 115 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&ps8640_pins>; + vdd12-supply = <&ps8640_fixed_1v2>; + vdd33-supply = <&mt6397_vgp2_reg>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ps8640_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + + ps8640_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; +}; + +&i2c1 { + clock-frequency = <1500000>; + status = "okay"; + + da9211: da9211@68 { + compatible = "dlg,da9211"; + reg = <0x68>; + interrupt-parent = <&pio>; + interrupts = <15 IRQ_TYPE_LEVEL_LOW>; + + regulators { + da9211_vcpu_reg: BUCKA { + regulator-name = "VBUCKA"; + regulator-min-microvolt = < 700000>; + regulator-max-microvolt = <1310000>; + regulator-min-microamp = <2000000>; + regulator-max-microamp = <4400000>; + regulator-ramp-delay = <10000>; + regulator-always-on; + regulator-allowed-modes = <0 1>; + }; + + da9211_vgpu_reg: BUCKB { + regulator-name = "VBUCKB"; + regulator-min-microvolt = < 700000>; + regulator-max-microvolt = <1310000>; + regulator-min-microamp = <2000000>; + regulator-max-microamp = <3000000>; + regulator-ramp-delay = <10000>; + }; + }; + }; +}; + +&i2c2 { + status = "okay"; + + tpm: tpm@20 { + compatible = "infineon,slb9645tt"; + reg = <0x20>; + powered-while-suspended; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + status = "okay"; + + touchscreen: touchscreen@10 { + compatible = "elan,ekth3500"; + reg = <0x10>; + interrupt-parent = <&pio>; + interrupts = <88 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c4 { + clock-frequency = <400000>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&trackpad_irq>; + + trackpad: trackpad@15 { + compatible = "elan,ekth3000"; + interrupt-parent = <&pio>; + interrupts = <117 IRQ_TYPE_LEVEL_LOW>; + reg = <0x15>; + vcc-supply = <&mt6397_vgp6_reg>; + wakeup-source; + }; +}; + +&mipi_tx0 { + status = "okay"; +}; + +&mmc0 { + status = "okay"; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + bus-width = <8>; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + cap-mmc-hw-reset; + hs400-ds-delay = <0x14015>; + mediatek,hs200-cmd-int-delay=<30>; + mediatek,hs400-cmd-int-delay=<14>; + mediatek,hs400-cmd-resp-sel-rising; + vmmc-supply = <&mt6397_vemc_3v3_reg>; + vqmmc-supply = <&mt6397_vio18_reg>; + assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; + non-removable; +}; + +&mmc1 { + status = "okay"; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_uhs>; + bus-width = <4>; + max-frequency = <200000000>; + cap-sd-highspeed; + sd-uhs-sdr50; + sd-uhs-sdr104; + cd-gpios = <&pio 1 GPIO_ACTIVE_LOW>; + vmmc-supply = <&mt6397_vmch_reg>; + vqmmc-supply = <&mt6397_vmc_reg>; +}; + +&mmc3 { + status = "okay"; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc3_pins_default>; + pinctrl-1 = <&mmc3_pins_uhs>; + bus-width = <4>; + max-frequency = <200000000>; + cap-sd-highspeed; + sd-uhs-sdr50; + sd-uhs-sdr104; + keep-power-in-suspend; + enable-sdio-wakeup; + cap-sdio-irq; + vmmc-supply = <&sdio_fixed_3v3>; + vqmmc-supply = <&mt6397_vgp3_reg>; + non-removable; + cap-power-off-card; + + #address-cells = <1>; + #size-cells = <0>; + + btmrvl: btmrvl@2 { + compatible = "marvell,sd8897-bt"; + reg = <2>; + interrupt-parent = <&pio>; + interrupts = <119 IRQ_TYPE_LEVEL_LOW>; + marvell,wakeup-pin = /bits/ 16 <0x0d>; + marvell,wakeup-gap-ms = /bits/ 16 <0x64>; + }; + + mwifiex: mwifiex@1 { + compatible = "marvell,sd8897"; + reg = <1>; + interrupt-parent = <&pio>; + interrupts = <38 IRQ_TYPE_LEVEL_LOW>; + marvell,wakeup-pin = <3>; + }; +}; + +&nor_flash { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&nor_gpio1_pins>; + bus-width = <8>; + max-frequency = <50000000>; + non-removable; + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + }; +}; + +&pio { + gpio-line-names = "EC_INT_1V8", + "SD_CD_L", + "ALC5514_IRQ", + "ALC5650_IRQ", + /* + * AP_FLASH_WP_L is crossystem ABI. Schematics + * call it SFWP_B. + */ + "AP_FLASH_WP_L", + "SFIN", + "SFCS0", + "SFHOLD", + "SFOUT", + "SFCK", + "WRAP_EVENT_S_EINT10", + "PMU_INT", + "I2S2_WS_ALC5650", + "I2S2_BCK_ALC5650", + "PWR_BTN_1V8", + "DA9212_IRQ", + "IDDIG", + "WATCHDOG", + "CEC", + "HDMISCK", + "HDMISD", + "HTPLG", + "MSDC3_DAT0", + "MSDC3_DAT1", + "MSDC3_DAT2", + "MSDC3_DAT3", + "MSDC3_CLK", + "MSDC3_CMD", + "USB_C0_OC_FLAGB", + "USBA_OC1_L", + "PS8640_1V2_ENABLE", + "THERM_ALERT_N", + "PANEL_LCD_POWER_EN", + "ANX7688_CHIP_PD_C", + "EC_IN_RW_1V8", + "ANX7688_1V_EN_C", + "USB_DP_HPD_C", + "TPM_DAVINT_N", + "MARVELL8897_IRQ", + "EN_USB_A0_PWR", + "USBA_A0_OC_L", + "EN_PP3300_DX_EDP", + "", + "SOC_I2C2_1V8_SDA_400K", + "SOC_I2C2_1V8_SCL_400K", + "SOC_I2C0_1V8_SDA_400K", + "SOC_I2C0_1V8_SCL_400K", + "EMMC_ID1", + "EMMC_ID0", + "MEM_CONFIG3", + "EMMC_ID2", + "MEM_CONFIG1", + "MEM_CONFIG2", + "BRD_ID2", + "MEM_CONFIG0", + "BRD_ID0", + "BRD_ID1", + "EMMC_DAT0", + "EMMC_DAT1", + "EMMC_DAT2", + "EMMC_DAT3", + "EMMC_DAT4", + "EMMC_DAT5", + "EMMC_DAT6", + "EMMC_DAT7", + "EMMC_CLK", + "EMMC_CMD", + "EMMC_RCLK", + "PLT_RST_L", + "LID_OPEN_1V8_L", + "AUDIO_SPI_MISO_R", + "", + "AC_OK_1V8", + "SD_DATA0", + "SD_DATA1", + "SD_DATA2", + "SD_DATA3", + "SD_CLK", + "SD_CMD", + "PWRAP_SPI0_MI", + "PWRAP_SPI0_MO", + "PWRAP_SPI0_CK", + "PWRAP_SPI0_CSN", + "", + "", + "WIFI_PDN", + "RTC32K_1V8", + "DISP_PWM0", + "TOUCHSCREEN_INT_L", + "", + "SRCLKENA0", + "SRCLKENA1", + "PS8640_MODE_CONF", + "TOUCHSCREEN_RESET_R", + "PLATFORM_PROCHOT_L", + "PANEL_POWER_EN", + "REC_MODE_L", + "EC_FW_UPDATE_L", + "ACCEL2_INT_L", + "HDMI_DP_INT", + "ACCELGYRO3_INT_L", + "ACCELGYRO4_INT_L", + "SPI_EC_CLK", + "SPI_EC_MI", + "SPI_EC_MO", + "SPI_EC_CSN", + "SOC_I2C3_1V8_SDA_400K", + "SOC_I2C3_1V8_SCL_400K", + "", + "", + "", + "", + "", + "", + "", + "PS8640_SYSRSTN_1V8", + "APIN_MAX98090_DOUT2", + "TP_INT_1V8_L_R", + "RST_USB_HUB_R", + "BT_WAKE_L", + "ACCEL1_INT_L", + "TABLET_MODE_L", + "", + "V_UP_IN_L_R", + "V_DOWN_IN_L_R", + "SOC_I2C1_1V8_SDA_1M", + "SOC_I2C1_1V8_SCL_1M", + "PS8640_PDN_1V8", + "MAX98090_LRCLK", + "MAX98090_BCLK", + "MAX98090_MCLK", + "APOUT_MAX98090_DIN", + "APIN_MAX98090_DOUT", + "SOC_I2C4_1V8_SDA_400K", + "SOC_I2C4_1V8_SCL_400K"; + + aud_i2s2: aud_i2s2 { + pins1 { + pinmux = <MT8173_PIN_128_I2S0_LRCK__FUNC_I2S1_WS>, + <MT8173_PIN_129_I2S0_BCK__FUNC_I2S1_BCK>, + <MT8173_PIN_130_I2S0_MCK__FUNC_I2S1_MCK>, + <MT8173_PIN_131_I2S0_DATA0__FUNC_I2S1_DO_1>, + <MT8173_PIN_12_EINT12__FUNC_I2S2_WS>, + <MT8173_PIN_13_EINT13__FUNC_I2S2_BCK>, + <MT8173_PIN_132_I2S0_DATA1__FUNC_I2S2_DI_2>; + bias-pull-down; + }; + }; + + bl_fixed_pins: bl_fixed_pins { + pins1 { + pinmux = <MT8173_PIN_32_UTXD2__FUNC_GPIO32>; + output-low; + }; + }; + + bt_wake_pins: bt_wake_pins { + pins1 { + pinmux = <MT8173_PIN_119_KPROW0__FUNC_GPIO119>; + bias-pull-up; + }; + }; + + disp_pwm0_pins: disp_pwm0_pins { + pins1 { + pinmux = <MT8173_PIN_87_DISP_PWM0__FUNC_DISP_PWM0>; + output-low; + }; + }; + + gpio_keys_pins: gpio_keys_pins { + volume_pins { + pinmux = <MT8173_PIN_123_KPCOL1__FUNC_GPIO123>, + <MT8173_PIN_124_KPCOL2__FUNC_GPIO124>; + bias-pull-up; + }; + + tablet_mode_pins { + pinmux = <MT8173_PIN_121_KPROW2__FUNC_GPIO121>; + bias-pull-up; + }; + }; + + hdmi_mux_pins: hdmi_mux_pins { + pins1 { + pinmux = <MT8173_PIN_36_DAISYNC__FUNC_GPIO36>; + }; + }; + + i2c1_pins_a: i2c1 { + da9211_pins { + pinmux = <MT8173_PIN_15_EINT15__FUNC_GPIO15>; + bias-pull-up; + }; + }; + + mmc0_pins_default: mmc0default { + pins_cmd_dat { + pinmux = <MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0>, + <MT8173_PIN_58_MSDC0_DAT1__FUNC_MSDC0_DAT1>, + <MT8173_PIN_59_MSDC0_DAT2__FUNC_MSDC0_DAT2>, + <MT8173_PIN_60_MSDC0_DAT3__FUNC_MSDC0_DAT3>, + <MT8173_PIN_61_MSDC0_DAT4__FUNC_MSDC0_DAT4>, + <MT8173_PIN_62_MSDC0_DAT5__FUNC_MSDC0_DAT5>, + <MT8173_PIN_63_MSDC0_DAT6__FUNC_MSDC0_DAT6>, + <MT8173_PIN_64_MSDC0_DAT7__FUNC_MSDC0_DAT7>, + <MT8173_PIN_66_MSDC0_CMD__FUNC_MSDC0_CMD>; + bias-pull-up; + }; + + pins_clk { + pinmux = <MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK>; + bias-pull-down; + }; + + pins_rst { + pinmux = <MT8173_PIN_68_MSDC0_RST___FUNC_MSDC0_RSTB>; + bias-pull-up; + }; + }; + + mmc1_pins_default: mmc1default { + pins_cmd_dat { + pinmux = <MT8173_PIN_73_MSDC1_DAT0__FUNC_MSDC1_DAT0>, + <MT8173_PIN_74_MSDC1_DAT1__FUNC_MSDC1_DAT1>, + <MT8173_PIN_75_MSDC1_DAT2__FUNC_MSDC1_DAT2>, + <MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3>, + <MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD>; + input-enable; + drive-strength = <MTK_DRIVE_4mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_10>; + }; + + pins_clk { + pinmux = <MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK>; + bias-pull-down; + drive-strength = <MTK_DRIVE_4mA>; + }; + + pins_insert { + pinmux = <MT8173_PIN_1_EINT1__FUNC_GPIO1>; + bias-pull-up; + }; + }; + + mmc3_pins_default: mmc3default { + pins_dat { + pinmux = <MT8173_PIN_22_MSDC3_DAT0__FUNC_MSDC3_DAT0>, + <MT8173_PIN_23_MSDC3_DAT1__FUNC_MSDC3_DAT1>, + <MT8173_PIN_24_MSDC3_DAT2__FUNC_MSDC3_DAT2>, + <MT8173_PIN_25_MSDC3_DAT3__FUNC_MSDC3_DAT3>; + input-enable; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_10>; + }; + + pins_cmd { + pinmux = <MT8173_PIN_27_MSDC3_CMD__FUNC_MSDC3_CMD>; + input-enable; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_10>; + }; + + pins_clk { + pinmux = <MT8173_PIN_26_MSDC3_CLK__FUNC_MSDC3_CLK>; + bias-pull-down; + drive-strength = <MTK_DRIVE_8mA>; + }; + }; + + mmc0_pins_uhs: mmc0 { + pins_cmd_dat { + pinmux = <MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0>, + <MT8173_PIN_58_MSDC0_DAT1__FUNC_MSDC0_DAT1>, + <MT8173_PIN_59_MSDC0_DAT2__FUNC_MSDC0_DAT2>, + <MT8173_PIN_60_MSDC0_DAT3__FUNC_MSDC0_DAT3>, + <MT8173_PIN_61_MSDC0_DAT4__FUNC_MSDC0_DAT4>, + <MT8173_PIN_62_MSDC0_DAT5__FUNC_MSDC0_DAT5>, + <MT8173_PIN_63_MSDC0_DAT6__FUNC_MSDC0_DAT6>, + <MT8173_PIN_64_MSDC0_DAT7__FUNC_MSDC0_DAT7>, + <MT8173_PIN_66_MSDC0_CMD__FUNC_MSDC0_CMD>; + input-enable; + drive-strength = <MTK_DRIVE_6mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins_clk { + pinmux = <MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK>; + drive-strength = <MTK_DRIVE_6mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_01>; + }; + + pins_ds { + pinmux = <MT8173_PIN_67_MSDC0_DSL__FUNC_MSDC0_DSL>; + drive-strength = <MTK_DRIVE_10mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_01>; + }; + + pins_rst { + pinmux = <MT8173_PIN_68_MSDC0_RST___FUNC_MSDC0_RSTB>; + bias-pull-up; + }; + }; + + mmc1_pins_uhs: mmc1 { + pins_cmd_dat { + pinmux = <MT8173_PIN_73_MSDC1_DAT0__FUNC_MSDC1_DAT0>, + <MT8173_PIN_74_MSDC1_DAT1__FUNC_MSDC1_DAT1>, + <MT8173_PIN_75_MSDC1_DAT2__FUNC_MSDC1_DAT2>, + <MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3>, + <MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD>; + input-enable; + drive-strength = <MTK_DRIVE_6mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_10>; + }; + + pins_clk { + pinmux = <MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK>; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + }; + + mmc3_pins_uhs: mmc3 { + pins_dat { + pinmux = <MT8173_PIN_22_MSDC3_DAT0__FUNC_MSDC3_DAT0>, + <MT8173_PIN_23_MSDC3_DAT1__FUNC_MSDC3_DAT1>, + <MT8173_PIN_24_MSDC3_DAT2__FUNC_MSDC3_DAT2>, + <MT8173_PIN_25_MSDC3_DAT3__FUNC_MSDC3_DAT3>; + input-enable; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_10>; + }; + + pins_cmd { + pinmux = <MT8173_PIN_27_MSDC3_CMD__FUNC_MSDC3_CMD>; + input-enable; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_10>; + }; + + pins_clk { + pinmux = <MT8173_PIN_26_MSDC3_CLK__FUNC_MSDC3_CLK>; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + }; + + nor_gpio1_pins: nor { + pins1 { + pinmux = <MT8173_PIN_6_EINT6__FUNC_SFCS0>, + <MT8173_PIN_7_EINT7__FUNC_SFHOLD>, + <MT8173_PIN_8_EINT8__FUNC_SFIN>; + input-enable; + drive-strength = <MTK_DRIVE_4mA>; + bias-pull-up; + }; + + pins2 { + pinmux = <MT8173_PIN_5_EINT5__FUNC_SFOUT>; + drive-strength = <MTK_DRIVE_4mA>; + bias-pull-up; + }; + + pins_clk { + pinmux = <MT8173_PIN_9_EINT9__FUNC_SFCK>; + input-enable; + drive-strength = <MTK_DRIVE_4mA>; + bias-pull-up; + }; + }; + + panel_fixed_pins: panel_fixed_pins { + pins1 { + pinmux = <MT8173_PIN_41_CMMCLK__FUNC_GPIO41>; + }; + }; + + ps8640_pins: ps8640_pins { + pins1 { + pinmux = <MT8173_PIN_92_PCM_CLK__FUNC_GPIO92>, + <MT8173_PIN_115_URTS0__FUNC_GPIO115>, + <MT8173_PIN_127_LCM_RST__FUNC_GPIO127>; + }; + }; + + ps8640_fixed_pins: ps8640_fixed_pins { + pins1 { + pinmux = <MT8173_PIN_30_URTS2__FUNC_GPIO30>; + }; + }; + + rt5650_irq: rt5650_irq { + pins1 { + pinmux = <MT8173_PIN_3_EINT3__FUNC_GPIO3>; + bias-pull-down; + }; + }; + + sdio_fixed_3v3_pins: sdio_fixed_3v3_pins { + pins1 { + pinmux = <MT8173_PIN_85_AUD_DAT_MOSI__FUNC_GPIO85>; + output-low; + }; + }; + + spi_pins_a: spi1 { + pins1 { + pinmux = <MT8173_PIN_0_EINT0__FUNC_GPIO0>; + bias-pull-up; + }; + + pins_spi { + pinmux = <MT8173_PIN_102_MSDC2_DAT2__FUNC_SPI_CK_1_>, + <MT8173_PIN_103_MSDC2_DAT3__FUNC_SPI_MI_1_>, + <MT8173_PIN_104_MSDC2_CLK__FUNC_SPI_MO_1_>, + <MT8173_PIN_105_MSDC2_CMD__FUNC_SPI_CS_1_>; + bias-disable; + }; + }; + + trackpad_irq: trackpad_irq { + pins1 { + pinmux = <MT8173_PIN_117_URXD3__FUNC_GPIO117>; + input-enable; + bias-pull-up; + }; + }; + + usb_pins: usb { + pins1 { + pinmux = <MT8173_PIN_101_MSDC2_DAT1__FUNC_GPIO101>; + output-high; + bias-disable; + }; + }; + + wifi_wake_pins: wifi_wake_pins { + pins1 { + pinmux = <MT8173_PIN_38_CONN_RST__FUNC_GPIO38>; + bias-pull-up; + }; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&pwrap { + pmic: mt6397 { + compatible = "mediatek,mt6397"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&pio>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + + clock: mt6397clock { + compatible = "mediatek,mt6397-clk"; + #clock-cells = <1>; + }; + + pio6397: pinctrl { + compatible = "mediatek,mt6397-pinctrl"; + pins-are-numbered; + gpio-controller; + #gpio-cells = <2>; + }; + + regulator: mt6397regulator { + compatible = "mediatek,mt6397-regulator"; + + mt6397_vpca15_reg: buck_vpca15 { + regulator-compatible = "buck_vpca15"; + regulator-name = "vpca15"; + regulator-min-microvolt = < 700000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + regulator-allowed-modes = <0 1>; + }; + + mt6397_vpca7_reg: buck_vpca7 { + regulator-compatible = "buck_vpca7"; + regulator-name = "vpca7"; + regulator-min-microvolt = < 700000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <115>; + regulator-always-on; + }; + + mt6397_vsramca15_reg: buck_vsramca15 { + regulator-compatible = "buck_vsramca15"; + regulator-name = "vsramca15"; + regulator-min-microvolt = < 700000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + }; + + mt6397_vsramca7_reg: buck_vsramca7 { + regulator-compatible = "buck_vsramca7"; + regulator-name = "vsramca7"; + regulator-min-microvolt = < 700000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + }; + + mt6397_vcore_reg: buck_vcore { + regulator-compatible = "buck_vcore"; + regulator-name = "vcore"; + regulator-min-microvolt = < 700000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + }; + + mt6397_vgpu_reg: buck_vgpu { + regulator-compatible = "buck_vgpu"; + regulator-name = "vgpu"; + regulator-min-microvolt = < 700000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <115>; + }; + + mt6397_vdrm_reg: buck_vdrm { + regulator-compatible = "buck_vdrm"; + regulator-name = "vdrm"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1400000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + }; + + mt6397_vio18_reg: buck_vio18 { + regulator-compatible = "buck_vio18"; + regulator-name = "vio18"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + }; + + mt6397_vtcxo_reg: ldo_vtcxo { + regulator-compatible = "ldo_vtcxo"; + regulator-name = "vtcxo"; + regulator-always-on; + }; + + mt6397_va28_reg: ldo_va28 { + regulator-compatible = "ldo_va28"; + regulator-name = "va28"; + }; + + mt6397_vcama_reg: ldo_vcama { + regulator-compatible = "ldo_vcama"; + regulator-name = "vcama"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vio28_reg: ldo_vio28 { + regulator-compatible = "ldo_vio28"; + regulator-name = "vio28"; + regulator-always-on; + }; + + mt6397_vusb_reg: ldo_vusb { + regulator-compatible = "ldo_vusb"; + regulator-name = "vusb"; + }; + + mt6397_vmc_reg: ldo_vmc { + regulator-compatible = "ldo_vmc"; + regulator-name = "vmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vmch_reg: ldo_vmch { + regulator-compatible = "ldo_vmch"; + regulator-name = "vmch"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vemc_3v3_reg: ldo_vemc3v3 { + regulator-compatible = "ldo_vemc3v3"; + regulator-name = "vemc_3v3"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vgp1_reg: ldo_vgp1 { + regulator-compatible = "ldo_vgp1"; + regulator-name = "vcamd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <240>; + }; + + mt6397_vgp2_reg: ldo_vgp2 { + regulator-compatible = "ldo_vgp2"; + regulator-name = "vcamio"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vgp3_reg: ldo_vgp3 { + regulator-compatible = "ldo_vgp3"; + regulator-name = "vcamaf"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vgp4_reg: ldo_vgp4 { + regulator-compatible = "ldo_vgp4"; + regulator-name = "vgp4"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vgp5_reg: ldo_vgp5 { + regulator-compatible = "ldo_vgp5"; + regulator-name = "vgp5"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3000000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vgp6_reg: ldo_vgp6 { + regulator-compatible = "ldo_vgp6"; + regulator-name = "vgp6"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <218>; + regulator-always-on; + }; + + mt6397_vibr_reg: ldo_vibr { + regulator-compatible = "ldo_vibr"; + regulator-name = "vibr"; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <218>; + }; + }; + + rtc: mt6397rtc { + compatible = "mediatek,mt6397-rtc"; + }; + + syscfg_pctl_pmic: syscfg_pctl_pmic@c000 { + compatible = "mediatek,mt6397-pctl-pmic-syscfg", + "syscon"; + reg = <0 0x0000c000 0 0x0108>; + }; + }; +}; + +&spi { + pinctrl-names = "default"; + pinctrl-0 = <&spi_pins_a>; + mediatek,pad-select = <1>; + status = "okay"; + /* clients */ + cros_ec: ec@0 { + compatible = "google,cros-ec-spi"; + reg = <0x0>; + spi-max-frequency = <12000000>; + interrupt-parent = <&pio>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + google,cros-ec-spi-msg-delay = <500>; + + i2c_tunnel: i2c-tunnel0 { + compatible = "google,cros-ec-i2c-tunnel"; + google,remote-bus = <0>; + #address-cells = <1>; + #size-cells = <0>; + + battery: sbs-battery@b { + compatible = "sbs,sbs-battery"; + reg = <0xb>; + sbs,i2c-retry-count = <2>; + sbs,poll-retry-count = <1>; + }; + }; + }; +}; + +&ssusb { + dr_mode = "host"; + wakeup-source; + vusb33-supply = <&mt6397_vusb_reg>; + status = "okay"; +}; + +&thermal { + bank0-supply = <&mt6397_vpca15_reg>; + bank1-supply = <&da9211_vcpu_reg>; +}; + +&uart0 { + status = "okay"; +}; + +&usb_host { + pinctrl-names = "default"; + pinctrl-0 = <&usb_pins>; + vusb33-supply = <&mt6397_vusb_reg>; + status = "okay"; +}; + +#include <arm/cros-ec-keyboard.dtsi> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index ccb8e88a60c5..f946cd079413 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -19,6 +19,7 @@ #include <dt-bindings/power/mt8173-power.h> #include <dt-bindings/reset/mt8173-resets.h> #include <dt-bindings/gce/mt8173-gce.h> +#include <dt-bindings/thermal/thermal.h> #include "mt8173-pinfunc.h" / { @@ -42,14 +43,18 @@ dpi0 = &dpi0; dsi0 = &dsi0; dsi1 = &dsi1; - mdp_rdma0 = &mdp_rdma0; - mdp_rdma1 = &mdp_rdma1; - mdp_rsz0 = &mdp_rsz0; - mdp_rsz1 = &mdp_rsz1; - mdp_rsz2 = &mdp_rsz2; - mdp_wdma0 = &mdp_wdma0; - mdp_wrot0 = &mdp_wrot0; - mdp_wrot1 = &mdp_wrot1; + mdp-rdma0 = &mdp_rdma0; + mdp-rdma1 = &mdp_rdma1; + mdp-rsz0 = &mdp_rsz0; + mdp-rsz1 = &mdp_rsz1; + mdp-rsz2 = &mdp_rsz2; + mdp-wdma0 = &mdp_wdma0; + mdp-wrot0 = &mdp_wrot0; + mdp-wrot1 = &mdp_wrot1; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; }; cluster0_opp: opp_table0 { @@ -162,6 +167,7 @@ <&apmixedsys CLK_APMIXED_MAINPLL>; clock-names = "cpu", "intermediate"; operating-points-v2 = <&cluster0_opp>; + capacity-dmips-mhz = <526>; }; cpu1: cpu@1 { @@ -176,6 +182,7 @@ <&apmixedsys CLK_APMIXED_MAINPLL>; clock-names = "cpu", "intermediate"; operating-points-v2 = <&cluster0_opp>; + capacity-dmips-mhz = <526>; }; cpu2: cpu@100 { @@ -190,6 +197,7 @@ <&apmixedsys CLK_APMIXED_MAINPLL>; clock-names = "cpu", "intermediate"; operating-points-v2 = <&cluster1_opp>; + capacity-dmips-mhz = <1024>; }; cpu3: cpu@101 { @@ -204,6 +212,7 @@ <&apmixedsys CLK_APMIXED_MAINPLL>; clock-names = "cpu", "intermediate"; operating-points-v2 = <&cluster1_opp>; + capacity-dmips-mhz = <1024>; }; idle-states { @@ -242,21 +251,21 @@ cpu_on = <0x84000003>; }; - clk26m: oscillator@0 { + clk26m: oscillator0 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; clock-output-names = "clk26m"; }; - clk32k: oscillator@1 { + clk32k: oscillator1 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32000>; clock-output-names = "clk32k"; }; - cpum_ck: oscillator@2 { + cpum_ck: oscillator2 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; @@ -272,19 +281,19 @@ sustainable-power = <1500>; /* milliwatts */ trips { - threshold: trip-point@0 { + threshold: trip-point0 { temperature = <68000>; hysteresis = <2000>; type = "passive"; }; - target: trip-point@1 { + target: trip-point1 { temperature = <85000>; hysteresis = <2000>; type = "passive"; }; - cpu_crit: cpu_crit@0 { + cpu_crit: cpu_crit0 { temperature = <115000>; hysteresis = <2000>; type = "critical"; @@ -292,16 +301,20 @@ }; cooling-maps { - map@0 { + map0 { trip = <&target>; - cooling-device = <&cpu0 0 0>, - <&cpu1 0 0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; contribution = <3072>; }; - map@1 { + map1 { trip = <&target>; - cooling-device = <&cpu2 0 0>, - <&cpu3 0 0>; + cooling-device = <&cpu2 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; contribution = <1024>; }; }; @@ -312,7 +325,7 @@ #address-cells = <2>; #size-cells = <2>; ranges; - vpu_dma_reserved: vpu_dma_mem_region { + vpu_dma_reserved: vpu_dma_mem_region@b7000000 { compatible = "shared-dma-pool"; reg = <0 0xb7000000 0 0x500000>; alignment = <0x1000>; @@ -365,7 +378,7 @@ reg = <0 0x10005000 0 0x1000>; }; - pio: pinctrl@10005000 { + pio: pinctrl@1000b000 { compatible = "mediatek,mt8173-pinctrl"; reg = <0 0x1000b000 0 0x1000>; mediatek,pctl-regmap = <&syscfg_pctl_a>; @@ -549,7 +562,7 @@ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>; clocks = <&infracfg CLK_INFRA_GCE>; clock-names = "gce"; - #mbox-cells = <3>; + #mbox-cells = <2>; }; mipi_tx0: mipi-dphy@10215000 { @@ -572,7 +585,7 @@ status = "disabled"; }; - gic: interrupt-controller@10220000 { + gic: interrupt-controller@10221000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; interrupt-parent = <&gic>; @@ -916,6 +929,9 @@ assigned-clocks = <&topckgen CLK_TOP_MM_SEL>; assigned-clock-rates = <400000000>; #clock-cells = <1>; + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, + <&gce 1 CMDQ_THR_PRIO_HIGHEST>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; }; mdp_rdma0: rdma@14001000 { @@ -996,6 +1012,7 @@ clocks = <&mmsys CLK_MM_DISP_OVL0>; iommus = <&iommu M4U_PORT_DISP_OVL0>; mediatek,larb = <&larb0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; }; ovl1: ovl@1400d000 { @@ -1006,6 +1023,7 @@ clocks = <&mmsys CLK_MM_DISP_OVL1>; iommus = <&iommu M4U_PORT_DISP_OVL1>; mediatek,larb = <&larb4>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; }; rdma0: rdma@1400e000 { @@ -1016,6 +1034,7 @@ clocks = <&mmsys CLK_MM_DISP_RDMA0>; iommus = <&iommu M4U_PORT_DISP_RDMA0>; mediatek,larb = <&larb0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; }; rdma1: rdma@1400f000 { @@ -1026,6 +1045,7 @@ clocks = <&mmsys CLK_MM_DISP_RDMA1>; iommus = <&iommu M4U_PORT_DISP_RDMA1>; mediatek,larb = <&larb4>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; }; rdma2: rdma@14010000 { @@ -1036,6 +1056,7 @@ clocks = <&mmsys CLK_MM_DISP_RDMA2>; iommus = <&iommu M4U_PORT_DISP_RDMA2>; mediatek,larb = <&larb4>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>; }; wdma0: wdma@14011000 { @@ -1046,6 +1067,7 @@ clocks = <&mmsys CLK_MM_DISP_WDMA0>; iommus = <&iommu M4U_PORT_DISP_WDMA0>; mediatek,larb = <&larb0>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; }; wdma1: wdma@14012000 { @@ -1056,6 +1078,7 @@ clocks = <&mmsys CLK_MM_DISP_WDMA1>; iommus = <&iommu M4U_PORT_DISP_WDMA1>; mediatek,larb = <&larb4>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>; }; color0: color@14013000 { @@ -1064,6 +1087,7 @@ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>; power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_COLOR0>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>; }; color1: color@14014000 { @@ -1072,6 +1096,7 @@ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>; power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_COLOR1>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>; }; aal@14015000 { @@ -1080,6 +1105,7 @@ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>; power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_AAL>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>; }; gamma@14016000 { @@ -1088,6 +1114,7 @@ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>; power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_GAMMA>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>; }; merge@14017000 { @@ -1193,6 +1220,8 @@ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>; power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_MUTEX_32K>; + mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>, + <CMDQ_EVENT_MUTEX1_STREAM_EOF>; }; larb0: larb@14021000 { @@ -1437,4 +1466,3 @@ }; }; }; - diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 97863adb7bc0..d946c1466c12 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -74,7 +74,7 @@ reg = <0x000>; enable-method = "psci"; capacity-dmips-mhz = <741>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; dynamic-power-coefficient = <84>; #cooling-cells = <2>; }; @@ -85,7 +85,7 @@ reg = <0x001>; enable-method = "psci"; capacity-dmips-mhz = <741>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; dynamic-power-coefficient = <84>; #cooling-cells = <2>; }; @@ -96,7 +96,7 @@ reg = <0x002>; enable-method = "psci"; capacity-dmips-mhz = <741>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; dynamic-power-coefficient = <84>; #cooling-cells = <2>; }; @@ -107,7 +107,7 @@ reg = <0x003>; enable-method = "psci"; capacity-dmips-mhz = <741>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; dynamic-power-coefficient = <84>; #cooling-cells = <2>; }; @@ -118,7 +118,7 @@ reg = <0x100>; enable-method = "psci"; capacity-dmips-mhz = <1024>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; dynamic-power-coefficient = <211>; #cooling-cells = <2>; }; @@ -129,7 +129,7 @@ reg = <0x101>; enable-method = "psci"; capacity-dmips-mhz = <1024>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; dynamic-power-coefficient = <211>; #cooling-cells = <2>; }; @@ -140,7 +140,7 @@ reg = <0x102>; enable-method = "psci"; capacity-dmips-mhz = <1024>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; dynamic-power-coefficient = <211>; #cooling-cells = <2>; }; @@ -151,7 +151,7 @@ reg = <0x103>; enable-method = "psci"; capacity-dmips-mhz = <1024>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; dynamic-power-coefficient = <211>; #cooling-cells = <2>; }; @@ -168,7 +168,15 @@ min-residency-us = <800>; }; - CLUSTER_SLEEP: cluster-sleep { + CLUSTER_SLEEP0: cluster-sleep@0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x01010001>; + entry-latency-us = <250>; + exit-latency-us = <400>; + min-residency-us = <1000>; + }; + CLUSTER_SLEEP1: cluster-sleep@1 { compatible = "arm,idle-state"; local-timer-stop; arm,psci-suspend-param = <0x01010001>; |