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| author | Feifei Xu <Feifei.Xu@amd.com> | 2017-11-27 12:29:29 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-12-06 20:48:25 +0300 |
| commit | 51199920a288b7a75eb1edf00c6b4834ec64b6ca (patch) | |
| tree | f5b8963572ff829da14b84a8382f3d37e404bffb | |
| parent | a146391bbbc546a0dda0eac60fdf32d6076817b5 (diff) | |
| download | linux-51199920a288b7a75eb1edf00c6b4834ec64b6ca.tar.xz | |
drm/amd/include:cleanup raven1 nbio header files.
Cleanup asic_reg/raven1/NBIO folder.
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c | 6 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_default.h (renamed from drivers/gpu/drm/amd/include/asic_reg/raven1/NBIO/nbio_7_0_default.h) | 0 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_offset.h (renamed from drivers/gpu/drm/amd/include/asic_reg/raven1/NBIO/nbio_7_0_offset.h) | 0 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_sh_mask.h (renamed from drivers/gpu/drm/amd/include/asic_reg/raven1/NBIO/nbio_7_0_sh_mask.h) | 0 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h | 6 |
6 files changed, 7 insertions, 7 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c index 8ddc44b503e9..1fb77174e02c 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c @@ -25,9 +25,9 @@ #include "nbio_v7_0.h" #include "soc15ip.h" -#include "raven1/NBIO/nbio_7_0_default.h" -#include "raven1/NBIO/nbio_7_0_offset.h" -#include "raven1/NBIO/nbio_7_0_sh_mask.h" +#include "nbio/nbio_7_0_default.h" +#include "nbio/nbio_7_0_offset.h" +#include "nbio/nbio_7_0_sh_mask.h" #include "vega10_enum.h" #define smnNBIF_MGCG_CTRL_LCLK 0x1013a05c diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index 1e5ca5345504..10cce51d31d2 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -55,7 +55,7 @@ #include "dcn/dcn_1_0_offset.h" #include "dcn/dcn_1_0_sh_mask.h" -#include "raven1/NBIO/nbio_7_0_offset.h" +#include "nbio/nbio_7_0_offset.h" #include "mmhub/mmhub_9_1_offset.h" #include "mmhub/mmhub_9_1_sh_mask.h" diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/NBIO/nbio_7_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_default.h index f5fc31ffcd73..f5fc31ffcd73 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/raven1/NBIO/nbio_7_0_default.h +++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_default.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/NBIO/nbio_7_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_offset.h index 435462294fbc..435462294fbc 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/raven1/NBIO/nbio_7_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_offset.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/NBIO/nbio_7_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_sh_mask.h index 88602479a1aa..88602479a1aa 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/raven1/NBIO/nbio_7_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_sh_mask.h diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h index 94961c7804d3..5fb38f611554 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h @@ -29,9 +29,9 @@ #include "asic_reg/mp/mp_10_0_offset.h" #include "asic_reg/mp/mp_10_0_sh_mask.h" -#include "asic_reg/raven1/NBIO/nbio_7_0_default.h" -#include "asic_reg/raven1/NBIO/nbio_7_0_offset.h" -#include "asic_reg/raven1/NBIO/nbio_7_0_sh_mask.h" +#include "asic_reg/nbio/nbio_7_0_default.h" +#include "asic_reg/nbio/nbio_7_0_offset.h" +#include "asic_reg/nbio/nbio_7_0_sh_mask.h" #include "asic_reg/raven1/THM/thm_10_0_default.h" #include "asic_reg/raven1/THM/thm_10_0_offset.h" |