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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2024 StarFive Technology Co., Ltd. */
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
core2 {
cpu = <&cpu2>;
};
core3 {
cpu = <&cpu3>;
};
};
};
cpu0: cpu@0 {
compatible = "starfive,dubhe-70", "riscv";
device_type = "cpu";
mmu-type = "riscv,sv48";
reg = <0x0>;
riscv,isa = "rv64imafdcbh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zba", "zbb",
"zbc", "zbs", "zicbom", "zicbop", "zicboz", "zicntr",
"zicond", "zicsr", "zifencei", "zihintpause",
"zihpm", "svinval", "svnapot", "svpbmt", "sscofpmf";
riscv,cbom-block-size = <64>;
riscv,cboz-block-size = <64>;
d-cache-block-size = <64>;
d-cache-sets = <512>;
d-cache-size = <32768>;
d-tlb-sets = <1>;
d-tlb-size = <16>;
i-cache-block-size = <64>;
i-cache-sets = <512>;
i-cache-size = <32768>;
i-tlb-sets = <1>;
i-tlb-size = <24>;
next-level-cache = <&l2_cache0>;
tlb-split;
cpu0_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu1: cpu@1 {
compatible = "starfive,dubhe-70", "riscv";
device_type = "cpu";
mmu-type = "riscv,sv48";
reg = <0x1>;
riscv,isa = "rv64imafdcbh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zba", "zbb",
"zbc", "zbs", "zicbom", "zicbop", "zicboz", "zicntr",
"zicond", "zicsr", "zifencei", "zihintpause",
"zihpm", "svinval", "svnapot", "svpbmt", "sscofpmf";
riscv,cbom-block-size = <64>;
riscv,cboz-block-size = <64>;
d-cache-block-size = <64>;
d-cache-sets = <512>;
d-cache-size = <32768>;
d-tlb-sets = <1>;
d-tlb-size = <16>;
i-cache-block-size = <64>;
i-cache-sets = <512>;
i-cache-size = <32768>;
i-tlb-sets = <1>;
i-tlb-size = <24>;
next-level-cache = <&l2_cache1>;
tlb-split;
cpu1_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu2: cpu@2 {
compatible = "starfive,dubhe-70", "riscv";
device_type = "cpu";
mmu-type = "riscv,sv48";
reg = <0x2>;
riscv,isa = "rv64imafdcbh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zba", "zbb",
"zbc", "zbs", "zicbom", "zicbop", "zicboz", "zicntr",
"zicond", "zicsr", "zifencei", "zihintpause",
"zihpm", "svinval", "svnapot", "svpbmt", "sscofpmf";
riscv,cbom-block-size = <64>;
riscv,cboz-block-size = <64>;
d-cache-block-size = <64>;
d-cache-sets = <512>;
d-cache-size = <32768>;
d-tlb-sets = <1>;
d-tlb-size = <16>;
i-cache-block-size = <64>;
i-cache-sets = <512>;
i-cache-size = <32768>;
i-tlb-sets = <1>;
i-tlb-size = <24>;
next-level-cache = <&l2_cache2>;
tlb-split;
cpu2_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu3: cpu@3 {
compatible = "starfive,dubhe-70", "riscv";
device_type = "cpu";
mmu-type = "riscv,sv48";
reg = <0x3>;
riscv,isa = "rv64imafdcbh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zba", "zbb",
"zbc", "zbs", "zicbom", "zicbop", "zicboz", "zicntr",
"zicond", "zicsr", "zifencei", "zihintpause",
"zihpm", "svinval", "svnapot", "svpbmt", "sscofpmf";
riscv,cbom-block-size = <64>;
riscv,cboz-block-size = <64>;
d-cache-block-size = <64>;
d-cache-sets = <512>;
d-cache-size = <32768>;
d-tlb-sets = <1>;
d-tlb-size = <16>;
i-cache-block-size = <64>;
i-cache-sets = <512>;
i-cache-size = <32768>;
i-tlb-sets = <1>;
i-tlb-size = <24>;
next-level-cache = <&l2_cache3>;
tlb-split;
cpu3_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
l2_cache0: cache-controller-0 {
compatible = "cache";
cache-block-size = <64>;
cache-level = <2>;
cache-sets = <2048>;
cache-size = <0x20000>;
cache-unified;
};
l2_cache1: cache-controller-1 {
compatible = "cache";
cache-block-size = <64>;
cache-level = <2>;
cache-sets = <2048>;
cache-size = <0x20000>;
cache-unified;
};
l2_cache2: cache-controller-2 {
compatible = "cache";
cache-block-size = <64>;
cache-level = <2>;
cache-sets = <2048>;
cache-size = <0x20000>;
cache-unified;
};
l2_cache3: cache-controller-3 {
compatible = "cache";
cache-block-size = <64>;
cache-level = <2>;
cache-sets = <2048>;
cache-size = <0x20000>;
cache-unified;
};
};
};
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