From d1bc4f65e25e3d1c70c9f60f9280bcb26f0014f4 Mon Sep 17 00:00:00 2001 From: Hal Feng Date: Wed, 31 Jul 2024 15:38:00 +0800 Subject: i2c: designware_i2c: Revert a part of commit "i2c:desigware-snps: add i2c clock config" This reverts a part of commit 83dd87455664 ("i2c:desigware-snps: add i2c clock config"). Signed-off-by: Hal Feng --- drivers/i2c/designware_i2c.c | 14 +++++--------- drivers/i2c/designware_i2c.h | 1 - 2 files changed, 5 insertions(+), 10 deletions(-) diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c index c1b3df9600..e57eed0f6c 100644 --- a/drivers/i2c/designware_i2c.c +++ b/drivers/i2c/designware_i2c.c @@ -775,14 +775,10 @@ int designware_i2c_of_to_plat(struct udevice *bus) if (ret) return ret; - ret = clk_get_bulk(bus, &priv->clks); - if (ret) - return ret; - - ret = clk_enable_bulk(&priv->clks); + ret = clk_enable(&priv->clk); if (ret && ret != -ENOSYS && ret != -ENOTSUPP) { - clk_release_bulk(&priv->clks); - dev_err(bus, "failed to enable bulk clock\n"); + clk_free(&priv->clk); + dev_err(bus, "failed to enable clock\n"); return ret; } #endif @@ -813,8 +809,8 @@ int designware_i2c_remove(struct udevice *dev) struct dw_i2c *priv = dev_get_priv(dev); #if CONFIG_IS_ENABLED(CLK) - clk_disable_bulk(&priv->clks); - clk_release_bulk(&priv->clks); + clk_disable(&priv->clk); + clk_free(&priv->clk); #endif return reset_release_bulk(&priv->resets); diff --git a/drivers/i2c/designware_i2c.h b/drivers/i2c/designware_i2c.h index d5aaef1d79..9b2349a0a2 100644 --- a/drivers/i2c/designware_i2c.h +++ b/drivers/i2c/designware_i2c.h @@ -204,7 +204,6 @@ struct dw_i2c { bool has_spk_cnt; #if CONFIG_IS_ENABLED(CLK) struct clk clk; - struct clk_bulk clks; #endif struct dw_i2c_speed_config config; }; -- cgit v1.2.3 From d4cb123cb3220f3cf0d1913c81400aa915b6b8f7 Mon Sep 17 00:00:00 2001 From: Hal Feng Date: Wed, 31 Jul 2024 15:45:21 +0800 Subject: clk: starfive: jh7110: Drop i2c core clock Enable i2c apb clock is enough, the core clock is redundant. Signed-off-by: Hal Feng --- arch/riscv/dts/jh7110.dtsi | 35 ++++++++++++++--------------------- drivers/clk/starfive/clk-jh7110.c | 21 --------------------- 2 files changed, 14 insertions(+), 42 deletions(-) diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi index f3f830f5f3..80d99ec64f 100644 --- a/arch/riscv/dts/jh7110.dtsi +++ b/arch/riscv/dts/jh7110.dtsi @@ -626,9 +626,8 @@ i2c0: i2c@10030000 { compatible = "snps,designware-i2c"; reg = <0x0 0x10030000 0x0 0x10000>; - clocks = <&clkgen JH7110_I2C0_CLK_CORE>, - <&clkgen JH7110_I2C0_CLK_APB>; - clock-names = "ref", "pclk"; + clocks = <&clkgen JH7110_I2C0_CLK_APB>; + clock-names = "pclk"; resets = <&rstgen RSTN_U0_DW_I2C_APB>; interrupts = <35>; #address-cells = <1>; @@ -639,9 +638,8 @@ i2c1: i2c@10040000 { compatible = "snps,designware-i2c"; reg = <0x0 0x10040000 0x0 0x10000>; - clocks = <&clkgen JH7110_I2C1_CLK_CORE>, - <&clkgen JH7110_I2C1_CLK_APB>; - clock-names = "ref", "pclk"; + clocks = <&clkgen JH7110_I2C1_CLK_APB>; + clock-names = "pclk"; resets = <&rstgen RSTN_U1_DW_I2C_APB>; interrupts = <36>; #address-cells = <1>; @@ -652,9 +650,8 @@ i2c2: i2c@10050000 { compatible = "snps,designware-i2c"; reg = <0x0 0x10050000 0x0 0x10000>; - clocks = <&clkgen JH7110_I2C2_CLK_CORE>, - <&clkgen JH7110_I2C2_CLK_APB>; - clock-names = "ref", "pclk"; + clocks = <&clkgen JH7110_I2C2_CLK_APB>; + clock-names = "pclk"; resets = <&rstgen RSTN_U2_DW_I2C_APB>; interrupts = <37>; #address-cells = <1>; @@ -665,9 +662,8 @@ i2c3: i2c@12030000 { compatible = "snps,designware-i2c"; reg = <0x0 0x12030000 0x0 0x10000>; - clocks = <&clkgen JH7110_I2C3_CLK_CORE>, - <&clkgen JH7110_I2C3_CLK_APB>; - clock-names = "ref", "pclk"; + clocks = <&clkgen JH7110_I2C3_CLK_APB>; + clock-names = "pclk"; resets = <&rstgen RSTN_U3_DW_I2C_APB>; interrupts = <48>; #address-cells = <1>; @@ -678,9 +674,8 @@ i2c4: i2c@12040000 { compatible = "snps,designware-i2c"; reg = <0x0 0x12040000 0x0 0x10000>; - clocks = <&clkgen JH7110_I2C4_CLK_CORE>, - <&clkgen JH7110_I2C4_CLK_APB>; - clock-names = "ref", "pclk"; + clocks = <&clkgen JH7110_I2C4_CLK_APB>; + clock-names = "pclk"; resets = <&rstgen RSTN_U4_DW_I2C_APB>; interrupts = <49>; #address-cells = <1>; @@ -691,9 +686,8 @@ i2c5: i2c5@12050000 { compatible = "snps,designware-i2c"; reg = <0x0 0x12050000 0x0 0x10000>; - clocks = <&clkgen JH7110_I2C5_CLK_CORE>, - <&clkgen JH7110_I2C5_CLK_APB>; - clock-names = "ref", "pclk"; + clocks = <&clkgen JH7110_I2C5_CLK_APB>; + clock-names = "pclk"; resets = <&rstgen RSTN_U5_DW_I2C_APB>; interrupts = <50>; #address-cells = <1>; @@ -704,9 +698,8 @@ i2c6: i2c@12060000 { compatible = "snps,designware-i2c"; reg = <0x0 0x12060000 0x0 0x10000>; - clocks = <&clkgen JH7110_I2C6_CLK_CORE>, - <&clkgen JH7110_I2C6_CLK_APB>; - clock-names = "ref", "pclk"; + clocks = <&clkgen JH7110_I2C6_CLK_APB>; + clock-names = "pclk"; resets = <&rstgen RSTN_U6_DW_I2C_APB>; interrupts = <51>; #address-cells = <1>; diff --git a/drivers/clk/starfive/clk-jh7110.c b/drivers/clk/starfive/clk-jh7110.c index 5311633c4f..f0b7571097 100644 --- a/drivers/clk/starfive/clk-jh7110.c +++ b/drivers/clk/starfive/clk-jh7110.c @@ -431,51 +431,30 @@ static int jh7110_clk_init(struct udevice *dev) starfive_clk_gate(priv->sys, "u0_dw_i2c_clk_apb", "apb0", SYS_OFFSET(JH7110_I2C0_CLK_APB))); - clk_dm(JH7110_I2C0_CLK_CORE, - starfive_clk_fix_factor(priv->sys, - "u0_dw_i2c_clk_core", "u0_dw_i2c_clk_apb", 1, 1)); clk_dm(JH7110_I2C1_CLK_APB, starfive_clk_gate(priv->sys, "u1_dw_i2c_clk_apb", "apb0", SYS_OFFSET(JH7110_I2C1_CLK_APB))); - clk_dm(JH7110_I2C1_CLK_CORE, - starfive_clk_fix_factor(priv->sys, - "u1_dw_i2c_clk_core", "u1_dw_i2c_clk_apb", 1, 1)); clk_dm(JH7110_I2C2_CLK_APB, starfive_clk_gate(priv->sys, "u2_dw_i2c_clk_apb", "apb0", SYS_OFFSET(JH7110_I2C2_CLK_APB))); - clk_dm(JH7110_I2C2_CLK_CORE, - starfive_clk_fix_factor(priv->sys, - "u2_dw_i2c_clk_core", "u2_dw_i2c_clk_apb", 1, 1)); clk_dm(JH7110_I2C3_CLK_APB, starfive_clk_gate(priv->sys, "u3_dw_i2c_clk_apb", "apb12", SYS_OFFSET(JH7110_I2C3_CLK_APB))); - clk_dm(JH7110_I2C3_CLK_CORE, - starfive_clk_fix_factor(priv->sys, - "u3_dw_i2c_clk_core", "u3_dw_i2c_clk_apb", 1, 1)); clk_dm(JH7110_I2C4_CLK_APB, starfive_clk_gate(priv->sys, "u4_dw_i2c_clk_apb", "apb12", SYS_OFFSET(JH7110_I2C4_CLK_APB))); - clk_dm(JH7110_I2C4_CLK_CORE, - starfive_clk_fix_factor(priv->sys, - "u4_dw_i2c_clk_core", "u4_dw_i2c_clk_apb", 1, 1)); clk_dm(JH7110_I2C5_CLK_APB, starfive_clk_gate(priv->sys, "u5_dw_i2c_clk_apb", "apb12", SYS_OFFSET(JH7110_I2C5_CLK_APB))); - clk_dm(JH7110_I2C5_CLK_CORE, - starfive_clk_fix_factor(priv->sys, - "u5_dw_i2c_clk_core", "u5_dw_i2c_clk_apb", 1, 1)); clk_dm(JH7110_I2C6_CLK_APB, starfive_clk_gate(priv->sys, "u6_dw_i2c_clk_apb", "apb12", SYS_OFFSET(JH7110_I2C6_CLK_APB))); - clk_dm(JH7110_I2C6_CLK_CORE, - starfive_clk_fix_factor(priv->sys, - "u6_dw_i2c_clk_core", "u6_dw_i2c_clk_apb", 1, 1)); /*QSPI*/ clk_dm(JH7110_QSPI_CLK_AHB, -- cgit v1.2.3