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2021-01-24reset: mtmips: add reset controller support for MediaTek MT7620 SoCWeijie Gao1-0/+35
This patch adds reset controller bits definition header file for MediaTek MT7620 SoC Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2021-01-24clk: add clock driver for MediaTek MT7620 SoCWeijie Gao1-0/+40
This patch adds a clock driver for MediaTek MT7620 SoC. This driver provides clock gate control as well as getting clock frequency for CPU/SYS/XTAL and some peripherals. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2021-01-23arm: dts: imx8mq: sync dts from Linux KernelPeng Fan1-1/+30
Sync dts from Linux Kernel commit f838f8d2b694cf9d524dc("mfd: ab8500-debugfs: Remove extraneous seq_putc") Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-01-23arm: dts: imx8mp: sync dts from Linux KernelPeng Fan1-3/+92
Sync dts from Linux Kernel commit f838f8d2b694cf9d524dc("mfd: ab8500-debugfs: Remove extraneous seq_putc") Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-01-23arm: dts: imx8mn: sync dts from Linux KernelPeng Fan1-3/+27
Sync dts from Linux Kernel commit f838f8d2b694cf9d524dc("mfd: ab8500-debugfs: Remove extraneous seq_putc") Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-01-22pinctrl: at91-pio4: implement drive strength supportEugen Hristev1-0/+4
Implement drive strength support, by preserving the same bindings as in Linux. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2021-01-22dt-bindings: pinctrl: at91-pio4: update license to SPDX styleEugen Hristev1-2/+1
Update license header to SPDX style Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2021-01-18reset: aspeed: Add AST2600 reset supportChia-Wei, Wang1-0/+70
Add controller reset support through the System Control Unit (SCU) of AST2600 SoC. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2021-01-18clk: aspeed: Add AST2600 clock supportRyan Chen1-0/+62
This patch adds the clock control driver for the AST2600 SoC. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
2021-01-18clk: mediatek: Add MT8183 clock driverFabien Parent1-0/+329
Add the topckgen, apmixedsys and infracfg clock driver for the MT8183 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com>
2021-01-18clk: Add Microchip PolarFire SoC clock driverPadmarao Begari1-0/+45
Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
2021-01-13Merge tag 'u-boot-amlogic-20210112' of ↵Tom Rini2-0/+27
https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic - sync amlogic GX & AXG DT to Linux 5.10 - Add new MESON_EE driver support for GXBB & AXG - Add support for Libretech-CC v2, Wetek Core2, Beelink GT-King/Pro boards - add driver for TDO tl070wsh30 panel driver - meson: isolate loading of socinfo - Add soc_rev to environment - Enable G12A support for saradc - Add correct mmcdev on VIM3(L) & Odroid-N2(C4) - Read MAC from fuses for VIM3 & VIM3L boards
2021-01-12dt-bindings: bus: ti-sysc: resync with Linux 5.9-rc7Dario Binacchi1-0/+6
Add support for PRUSS SYSC type: The PRUSS module has a SYSCFG which is unique. The SYSCFG has two additional unique fields called STANDBY_INIT and SUB_MWAIT in addition to regular IDLE_MODE and STANDBY_MODE fields. Add the bindings for this new sysc type. Add support for MCAN on dra76x: The dra76x MCAN generic interconnect module has a its own format for the bits in the control registers. Signed-off-by: Dario Binacchi <dariobin@libero.it>
2021-01-11ARM: dts: sync Amlogic GX & AXG from Linux 5.10-rc1Neil Armstrong2-0/+27
Synced from Linux commit 3650b228f83a ("Linux 5.10-rc1") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-12-26imx: imx8mm: Update clock bindings headerAdam Ford1-1/+27
Import clock bindings header file from Linux 5.10-rc6 Signed-off-by: Adam Ford <aford173@gmail.com> Acked-by: Peng Fan <peng.fan@nxp.com>
2020-11-25reset: stm32: Add support of MCU HOLD BOOTPatrick Delaunay1-0/+1
Handle the register RCC_MP_GCR without SET/CLR registers but with a direct access to bit BOOT_MCU: - deassert => set the bit: The MCU will not be in HOLD_BOOT - assert => clear the bit: The MCU will be set in HOLD_BOOT With this patch the RCC driver handles the MCU_HOLD_BOOT_R value added in binding stm32mp1-resets.h Cc: Fabien DESSENNE <fabien.dessenne@st.com> Cc: Arnaud POULIQUEN <arnaud.pouliquen@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-11-17sunxi: DT: A64: update device tree filesSamuel Holland3-1/+7
Import updated device trees from Linux tag v5.9. This picks up new hardware (PinePhone, PineTab); and it drops the U-Boot specific DTSI files for the Pinebook and the Teres-I, since the ANX6345 bridge is now supported upstream. A couple of headers needed updates for recently-added hardware support. Acked-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-10-29Merge tag 'xilinx-for-v2021.01-v2' of ↵Tom Rini2-0/+165
https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2021.01-v2 common: - Add support for 64bit loadables from SPL xilinx: - Update documentation and record ownership - Enable eeprom board detection based legacy and fru formats - Add support for FRU format microblaze: - Optimize low level ASM code - Enable SPI/I2C - Enable distro boot zynq: - Add support for Zturn V5 zynqmp: - Improve silicon detection code - Enable several kconfig options - Align DT with the latest state - Enabling security commands - Enable and support FPGA loading from SPL - Optimize xilinx_pm_request() calling versal: - Some DTs/Kconfig/defconfig alignments - Add binding header for clock and power zynq-sdhci: - Add support for tap delay programming zynq-spi/zynq-qspi: - Use clock framework for getting clocks xilinx-spi: - Fix some code issues (unused variables) serial: - Check return value from clock functions in pl01x
2020-10-28drivers: Add a new framework for multiplexer devicesJean-Jacques Hiblot1-0/+17
Add a new subsystem that handles multiplexer controllers. The API is the same as in Linux. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Pratyush Yadav <p.yadav@ti.com> [trini: Update some error calls to use different functions or pass correct arguments] Signed-off-by: Tom Rini <trini@konsulko.com>
2020-10-27dt-bindings: arm64: versal: Add clk and power headersMichal Simek2-0/+165
Add power and reset headers to be sources by Versal dtses. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-10-22reset: ast2500: Use SCU for reset controlChia-Wei, Wang1-34/+39
The System Control Unit (SCU) controller of Aspeed SoCs provides the reset control for each peripheral. This patch refactors the reset method to leverage the SCU reset control. Thus the driver dependency on watchdog including dedicated WDT API and reset flag encoding can be eliminated. The Kconfig description is also updated accordingly. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-10-20arm: dts: r8a774c0: Import DTS from Linux 5.9Lad Prabhakar2-0/+86
Import R8A774C0 (RZ/G2E) SoC DTSI and headers from Linux 5.9 commit bbf5c979011a ("Linux 5.9"). Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
2020-10-08pinctrl: Add support for Kendryte K210 FPIOASean Anderson1-0/+277
The Fully-Programmable Input/Output Array (FPIOA) device controls pin multiplexing on the K210. The FPIOA can remap any supported function to any multifunctional IO pin. It can also perform basic GPIO functions, such as reading the current value of a pin. However, GPIO functionality remains largely unimplemented (in favor of the dedicated GPIO peripherals). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-08test: pinmux: Add test for pin muxingSean Anderson1-0/+19
This extends the pinctrl-sandbox driver to support pin muxing, and adds a test for that behaviour. The test is done in C and not python (like the existing tests for the pinctrl uclass) because it needs to call pinctrl_select_state. Another option could be to add a command that invokes pinctrl_select_state and then test everything in test/py/tests/test_pinmux.py. The pinctrl-sandbox driver now mimics the way that many pinmux devices work. There are two groups of pins which are muxed together, as well as four pins which are muxed individually. I have tried to test all normal paths. However, very few error cases are explicitly checked for. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-06Merge tag 'u-boot-amlogic-20201005' of ↵Tom Rini4-1/+31
https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic - generate unique mac address from SoC serial on S400 board - Add USB support for GXL and AXG SoCs - Update Gadget code to use the new GXL and AXG USB glue driver - Add a VIM3 board support to add dynamic PCIe enable in OS DT - Fix AXG pinmux with requesting GPIOs - Add missing GPIOA_18 for AXG pinctrl - Add Amlogic PWM driver
2020-10-05ARM: dts: sync amlogic G12A/SM1 DT from Linux 5.9-rc1Neil Armstrong2-0/+12
This imports the G12A & SM1 SoC and boards DT changes from the Linux commit 9123e3a74ec7 ("Linux 5.9-rc1"). Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-10-05ARM: dts: sync amlogic AXG/GXL/GXM DT from Linux 5.8-rc1Neil Armstrong2-1/+19
This imports the AXG, GXL & GXM SoC and boards DT changes from the Linux commit b3a9e3b9622a ("Linux 5.8-rc1"). This change also removes GXL & GXM u-boot.dtsi hacks for USB gadget. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-10-05Merge tag 'u-boot-atmel-2021.01-a' of ↵Tom Rini1-0/+22
https://gitlab.denx.de/u-boot/custodians/u-boot-atmel into next First set of u-boot-atmel features for 2021.01 cycle: This feature set includes a new CPU driver for at91 family, new driver for PIT64B hardware timer, support for new at91 family SoC named sama7g5 which adds: clock support, including conversion of the clock tree to CCF; SoC support in mach-at91, pinctrl and mmc drivers update. The feature set also includes updates for mmc driver and some other minor fixes and features regarding building without the old Atmel PIT and the possibility to read a secondary MAC address from a second i2c EEPROM.
2020-10-01Merge branch 'next' of git://git.denx.de/u-boot-sh into nextTom Rini6-53/+223
2020-09-30riscv: clk: Add CLINT clock to kendryte clock driverSean Anderson1-0/+1
Another "virtual" clock (in the sense that it isn't configurable). This could possibly be done as a clock in the device tree, but I think this is a bit cleaner. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-09-26arm: dts: r8a774e1: Import DTS from Linux 5.9-rc4Biju Das2-0/+95
Import R8A774E1 (RZ/G2H) SoC DTSI and headers from upstream Linux kernel 5.9-rc4 commit f4d51dffc6c0 ("Linux 5.9-rc4") Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-09-26arm: dts: r8a774b1: Import DTS from Linux 5.9-rc4Biju Das2-0/+83
Import R8A774B1 (RZ/G2N) SoC DTSI and headers from upstream Linux kernel 5.9-rc4 commit f4d51dffc6c0 ("Linux 5.9-rc4") Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-09-26arm: dts: r8a774a1: Import DTS from Linux 5.9-rc4Biju Das2-53/+45
Synchronize RZ/G2M SoC DTs with mainline Linux 5.9-rc4 commit f4d51dffc6c0 ("Linux 5.9-rc4") Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-09-24Merge tag 'xilinx-for-v2021.01' of ↵Tom Rini1-0/+40
https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2021.01 arm64: - Support for bigger U-Boot images compiled with PIE microblaze: - Extend support for LE/BE systems zynqmp: - Refactor silicon ID detection code with using firmware interface - Add support for saving variables based on bootmode zynqmp-r5: - Fix MPU mapping and defconfig setting. xilinx: - Minor driver changes: names alignment - Enable UBIFS - Minor DT and macros fixes - Fix boot with appended DT - Fix distro boot cmd: - pxe: Add fixing for platforms with manual relocation support clk: - fixed_rate: Add DM flag to support early boot on r5 fpga: - zynqmppl: Use only firmware interface and enable SPL build serial: - uartlite: Enable for ARM systems and support endians mmc: - zynq: Fix indentation net: - gem: Support for multiple phys - emac: Fix 64bit support and enable it for arm64 kconfig: - Setup default values for Xilinx platforms - Fix dependecies for Xilinx drivers - Source board Kconfig only when platform is enabled - Fix FPGA Kconfig entry with SPL - Change some defconfig values bindings: - Add binding doc for vsc8531
2020-09-23include: dt-bindings: Add MSCC headerHarini Katakam1-0/+40
Add MSCC header with delay definitions for VSC8531 and associated family devices. Signed-off-by: Harini Katakam <harini.katakam@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-22clk: at91: add pre-requisite headers for AT91 clock architectureClaudiu Beznea1-0/+22
Add pre-requisite headers for AT91 clock architecture. These are based on already present files on Linux and will be used by following commits for AT91 CCF clock drivers. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-09-18reset: Add IPQ40xx reset controller driverRobert Marko1-0/+92
On Qualcomm IPQ40xx SoC series, GCC clock IP also handles the resets. So since this will be needed by further drivers, lets add a driver for the reset controller. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-09-09dt-bindings: clock: import Qualcomm IPQ4019 bindingsRobert Marko1-0/+96
Import Qualcomm IPQ4019 GCC bindings from Linux. This will enable using bindings instead of raw clock numbers both in the driver and DTS like Linux does. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-09-09cosmetic: aspeed: Modify for SPDX-LicenseRyan Chen1-1/+1
Modify SPDX-License for furture patch warning Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Reviewed-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
2020-09-09clock:aspeed: Sync with Linux kernel clock header defineRyan Chen1-28/+40
v2: modify title description aspeed:clock -> clock:aspeed Use kernel include/dt-bindings/clock/aspeed-clock.h define for clock driver. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Reviewed-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
2020-09-09cosmetic: aspeed: ast2500: Rename clock headerRyan Chen1-0/+0
Rename the ast2500-scu.h to aspeed-clock.h. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Reviewed-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org>
2020-08-20arm: dts: mt7622: add SATA reset constantsFrank Wunderlich1-1/+4
add reset constants used for SATA to header file Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2020-08-05dt-bindings: Sync include/dt-bindings/phy/phy.h from LinuxMichal Simek1-0/+4
Add 4 new phy types which are present in Linux kernel. DP and SGMII types are used on Xilinx ZynqMP devices. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-08-04Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscvTom Rini1-0/+19
- add DM based reset driver for SiFive SoC's.
2020-08-04dt-bindings: prci: add indexes for reset signals available in prciSagar Shrikant Kadam1-0/+19
Add bit indexes for reset signals within the PRCI module on FU540-C000 SoC. The DDR and ethernet sub-system's have reset signals indicated by these reset indexes. Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-08-03clk: clk_octeon: Add simple MIPS Octeon clock driverStefan Roese1-0/+12
This patch adds a simple clock driver for the Marvell Octeon MIPS SoC family. Its for IO clock rate passing via DT in some of the Octeon driver, like I2C. So that we don't need to use the non-mainline API octeon_get_io_clock(). Signed-off-by: Stefan Roese <sr@denx.de> Cc: Lukasz Majewski <lukma@denx.de>
2020-07-29dt-bindings: pinctrl: add ns3 pads definitionRayagonda Kokatanur1-0/+41
Add NS3 pads definitions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-29dt-bindings: memory: ns3: add ddr memory definitionRayagonda Kokatanur1-1/+30
Add ddr memory definitions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-29dt-bindings: memory: ns3: add memory definitionsRayagonda Kokatanur1-0/+34
Add NS3 memory definitions. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-25ARM: dts: r8a774a1: Import DTS from Linux 5.8-rc1Adam Ford2-0/+98
This patch imports the device tree and required bindings to permit the device tree to build for the R8Z774A1 (RZ/G2M). Signed-off-by: Adam Ford <aford173@gmail.com>
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