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2021-05-12ram: k3-ddrss: Introduce support for AM642 SoCsDave Gerlach20-0/+23490
Introduce support for the AM64 DDRSS controller which uses the 16bit variation of the controller. This controller shares much functionality with the existing J721e support, so this patch introduces only the new code needed for am64 specific support from "_16bit_" files with headers under "16bit/" include path/. Also add a CONFIG_K3_AM64_DDRSS option to the choice required for use with CONFIG_K3_DDRSS to allow selecting AM64 support. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12ram: k3-ddrss: Introduce common driver with J7 SoC supportDave Gerlach27-3849/+3675
Introduce a new version of the ddr driver which has the ability to support different variations of the controller. Also introduce support for the 32bit variation of the controller which is what was already supported by the previous version used for J721e and J7200. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12ram: k3-ddrss: Introduce top-level CONFIG_K3_DDRSSDave Gerlach2-2/+11
Create a new CONFIG_K3_DDRSS option to select the common parts of the k3-ddrss driver. Also introduce a choice that depends on the top level option to select CONFIG_K3_J721E_DDRSS for j721e support, and update corresponding Kconfig as required. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12ram: k3-j721e: Rename to k3-ddrssDave Gerlach20-1/+1
Rename the k3-j721e folder under drivers/ram to k3-ddrss in preparation of introducing additional support for other platforms to the same driver. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12ram: k3-j721e: lpddr4_ctl_regs: Fix checkpatch issue for typesDave Gerlach1-1514/+1514
Use Linux style u32 instead of uint32_t. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12ram: k3-j721e: lpddr4_pi_macros: Fix indentation issuesDave Gerlach1-2801/+2801
Fix the indentation for certain macros to be consistent with the other macros in the file, as the existing indentation does not make sense in many places. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12ram: k3-j721e: lpddr4_phy_core_macros: Fix indentation issuesDave Gerlach1-694/+694
Fix the indentation for certain macros to be consistent with the other macros in the file, as the existing indentation does not make sense in many places. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12ram: k3-j721e: lpddr4_ddr_controller_macros: Fix indentation issuesDave Gerlach1-3681/+3681
Fix the indentation for certain macros to be consistent with the other macros in the file, as the existing indentation does not make sense in many places. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12ram: k3-j721e: lpddr4_data_slice_3_macros: Fix indentation issuesDave Gerlach1-677/+677
Fix the indentation for certain macros to be consistent with the other macros in the file, as the existing indentation does not make sense in many places. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12ram: k3-j721e: lpddr4_data_slice_2_macros: Fix indentation issuesDave Gerlach1-677/+677
Fix the indentation for certain macros to be consistent with the other macros in the file, as the existing indentation does not make sense in many places. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12ram: k3-j721e: lpddr4_data_slice_1_macros: Fix indentation issuesDave Gerlach1-677/+677
Fix the indentation for certain macros to be consistent with the other macros in the file, as the existing indentation does not make sense in many places. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12ram: k3-j721e: lpddr4_data_slice_0_macros: Fix indentation issuesDave Gerlach1-717/+717
Fix the indentation for certain macros to be consistent with the other macros in the file, as the existing indentation does not make sense in many places. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12ram: k3-j721e: lpddr4_address_slice_0_macros: Fix indentation issuesDave Gerlach1-167/+167
Fix the indentation for certain macros to be consistent with the other macros in the file, as the existing indentation does not make sense in many places. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12mailbox: k3-sec-proxy: Extend valid thread IDsDave Gerlach1-9/+1
AM64x uses a different thread mapping that existing K3 SoCs, so update the valid thread ID list to include those used for AM64x. Also remove the comment identifying the purpose of each thread ID. The purpose of the thread ID is specified when describing the threads in the device tree and the same ID can mean different things on different SoCs, so the comment is not useful. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12mmc: sdhci_am654: Add Support for TI's AM642 SoCDave Gerlach1-0/+18
Add support for the controller present on the AM642 SoC. There are instances: sdhci0: 8bit bus width, max 400 MBps sdhci1: 4bit bus width, max 100 MBps Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12Revert "fdt: translate address if #size-cells = <0>"Dario Binacchi5-24/+13
This reverts commit d64b9cdcd475eb7f07b49741ded87e24dae4a5fc. As pointed by [1] and [2], the reverted patch made every DT 'reg' property translatable. What the patch was trying to fix was fixed in a different way from previously submitted patches which instead of correcting the generic address translation function fixed the issue with appropriate platform code. [1] https://patchwork.ozlabs.org/project/uboot/patch/1614324949-61314-1-git-send-email-bmeng.cn@gmail.com/ [2] https://lore.kernel.org/linux-clk/20210402192054.7934-1-dariobin@libero.it/T/ Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-05-12clk: ti: am3-dpll: use custom API for memory accessDario Binacchi1-33/+53
Using the custom TI functions required not only replacing common memory access functions but also rewriting the routines used to set bypass and lock states. As for readl() and writel(), they also required the address of the register to be accessed, a parameter that is hidden by the TI clk module. Signed-off-by: Dario Binacchi <dariobin@libero.it>
2021-05-12clk: ti: gate: use custom API for memory accessDario Binacchi1-11/+12
Replaces the common memory access functions used by the driver with the ones exported from the TI clk module. Signed-off-by: Dario Binacchi <dariobin@libero.it>
2021-05-12clk: ti: change clk_ti_latch() signatureDario Binacchi4-24/+28
The clock access functions exported by the clk header use the struct clk_ti_reg parameter to get the address of the register. This must also apply to clk_ti_latch(). Changes to TI's clk-mux and clk-divider drivers prevented the patch from generating compile errors. Signed-off-by: Dario Binacchi <dariobin@libero.it>
2021-05-12clk: ti: add custom API for memory accessDario Binacchi2-0/+98
As pointed by [1] and [2], commit d64b9cdcd4 ("fdt: translate address if #size-cells = <0>") is wrong: - It makes every 'reg' DT property translatable. It changes the address translation so that for an I2C 'reg' address you'll get back as reg the I2C controller address + reg value. - The quirk must be fixed with platform code. The clk_ti_get_reg_addr() is the platform code able to make the correct address translation for the AM33xx clocks registers. Its implementation was inspired by the Linux Kernel code. [1] https://patchwork.ozlabs.org/project/uboot/patch/1614324949-61314-1-git-send-email-bmeng.cn@gmail.com/ [2] https://lore.kernel.org/linux-clk/20210402192054.7934-1-dariobin@libero.it/T/ Signed-off-by: Dario Binacchi <dariobin@libero.it>
2021-05-11Merge tag 'u-boot-imx-20210502' of ↵Tom Rini3-9/+25
https://gitlab.denx.de/u-boot/custodians/u-boot-imx u-boot-imx-20210502 ------------------- - mx6: fixes for Ventana - local fixes from maintainer - imx7d: Ronetix's iMX7-CM - imx8: Ronetix iMX8MQ-CM Engicam i.Core MX8M Compulab iot-gate-imx8 - Fixes i.MX8 documentation - Fixes phy usage with fec
2021-05-11DM: DM_MMC migration is now mandatory for non-SPLTom Rini1-0/+2
As it has been now two years past the migration deadline, it is required to have migrated. Remove the check from the Makefile and rework some of the Kconfig logic slightly to get the functional dependencies of DM_MMC / BLK right in both the SPL and non-SPL case. Signed-off-by: Tom Rini <trini@konsulko.com>
2021-05-11ata: Make LIBATA means AHCI is enabled mandatory.Tom Rini1-2/+4
The migration deadline for having LIBATA mean that AHCI is also enabled was v2019.07. As that has long since passed, adjust the Kconfig dependencies. Signed-off-by: Tom Rini <trini@konsulko.com>
2021-05-07Merge https://source.denx.de/u-boot/custodians/u-boot-riscvTom Rini1-2/+8
2021-05-05atcspi200: Add timeout mechanism in spi_xfer()Dylan Jhong1-2/+8
Adding timeout mechanism to avoid spi driver from stucking in the while loop in __atcspi200_spi_xfer(). Signed-off-by: Dylan Jhong <dylan@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
2021-05-04sysinfo: Add gpio-sysinfo driverSean Anderson3-0/+150
This uses the newly-added dm_gpio_get_values_as_int_base3 function to implement a sysinfo device. The revision map is stored in the device tree. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-05-04sysinfo: Require that sysinfo_detect be called before other methodsSean Anderson1-1/+28
This has the uclass enforce calling detect() before other methods. This allows drivers to cache information in detect() and perform (cheaper) retrieval in the other accessors. This also modifies the only instance where this sequencing was not followed. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-05-04sysinfo: Use global sysinfo IDs for existing sysinfo driversSean Anderson2-4/+6
Since 07c9e683a4 ("smbios: Allow a few values to come from sysinfo") there are common global sysinfo IDs. This patch moved existing IDs above SYSINFO_ID_USER. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-05-04dm: gpio: Fix gpio_get_list_count failing with livetreeSean Anderson1-3/+3
of_parse_phandle_with_args (called by dev_read_phandle_with_args) does not support getting the length of a phandle list by using the index -1. Instead, use dev_count_phandle_with_args which supports exactly this use-case. Fixes: 8558217153 ("gpio: Convert to use APIs which support live DT") Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-05-02pci: imx: disable imx6sdl LTSSM upon driver removeTim Harvey1-1/+1
commit 6ecbe1375671 ("drivers: pci: imx: add imx_pcie_remove function") attempted to resolve an issue caused by MX6QDL not having a proper intneral PCIe core reset and thus hanging during kernel init if the bootloader had enabled PCI. The issue exists for IMX6Q, IMX6D, IXM6S, and IMX6DL. Fix the case for IMX6S and IMX6DL getting missed. This fixes IMX6S and IMX6DL with PCI enabled in U-Boot booting for Linux v4.11+. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2021-05-02net: fec: Only unregister MII bus if we registered itSean Anderson1-2/+6
If we fail to probe for whatever reason, we cannot unregister/free the MII bus unless we registered it with fec_get_miibus. This fixes FECs sharing an MDIO bus from destroying it, preventing the other FEC from using it. Fixes: 6a895d039b ("net: Update eQos driver and FEC driver to use eth phy interfaces") Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-05-02net: fec: Don't use disabled physSean Anderson1-6/+9
If a phy is disabled, don't use it. This matches Linux's behavior. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-05-02pci: pci-uclass: Add board_pci_fixup_dev for DM_PCITim Harvey1-0/+6
Add a board_pci_fixup_dev weak function to allow PCI device fixups during enumeration. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-05-02pci: Update the highest subordinate bus number for bridge setupMasami Hiramatsu1-0/+3
Update the highest subordinate bus number after probing the devices under the bus for setting up the bridge correctly. The commit 42f3663a3f67 ("pci: Update to use new sequence numbers") removed this but it is required if a PCIe bridge is under the bus. Fixes: 42f3663a3f67 ("pci: Update to use new sequence numbers") Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-04-30Merge tag 'dm-pull-29apr21' of ↵Tom Rini7-24/+17
https://source.denx.de/u-boot/custodians/u-boot-dm buildman environment fix binman FMAP improvements minor test improvements and fixes minor dm improvements
2021-04-29Merge tag 'xilinx-for-v2021.07-rc2' of ↵Tom Rini3-6/+3
https://source.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2021.07-rc2 xilinx: - Enable saving variables based on bootmode - Cleanup usb dfu setup and wire it up with usb bootmode - Fix bootscript address logic - Remove GD references (spi, Versal) - Enable capsule update clk: - Small Kconfig fix net: - Fix gmii2rgmii bridge binding usb: - Propagate error (dfu gadget)
2021-04-29spi: zynqmp: Remove gd referenceMichal Simek1-3/+0
gd is not used in this file that's why doesn't make sense to declare it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-04-29Merge https://source.denx.de/u-boot/custodians/u-boot-cfi-flashTom Rini1-5/+5
- mtd: cfi: Fix PPB lock status readout (Marek)
2021-04-29Merge https://source.denx.de/u-boot/custodians/u-boot-marvellTom Rini10-1280/+335
- Add base support for Marvell OcteonTX2 CN9130 CRB (mostly done by Kostya) - Sync Armada 3k/7k/8k SERDES code with Marvell version (misc Marvell authors) - pci-aardvark: Fix processing PIO transfers (Pali)
2021-04-29dm: core: Add size operations on device tree referencesChen Guanqiao1-0/+11
Add functions to add size of addresses in the device tree using ofnode references. If the size is not set, return FDT_SIZE_T_NONE. Signed-off-by: Chen Guanqiao <chenguanqiao@kuaishou.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-04-29dm: core: Fix uninitialized return value from dm_scan_fdt_nodeSean Anderson1-1/+1
If there are no nodes or if all nodes are disabled, this function would return err without setting it first. Fix this by initializing err to zero. Fixes: 94f7afdf7e ("dm: core: Ignore disabled devices when binding") Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-04-29dm: core: Add address translation in fdt_get_resourcePatrick Delaunay5-23/+5
Today of_address_to_resource() is called only in ofnode_read_resource() for livetree support and fdt_get_resource() is called when livetree is not supported. The fdt_get_resource() doesn't do the address translation so when it is required, but the address translation is done by ofnode_read_resource() caller, for example in drivers/firmware/scmi/smt.c::scmi_dt_get_smt_buffer() { ... ret = ofnode_read_resource(args.node, 0, &resource); if (ret) return ret; faddr = cpu_to_fdt32(resource.start); paddr = ofnode_translate_address(args.node, &faddr); ... The both behavior should be aligned and the address translation must be called in fdt_get_resource() and removed for each caller. Fixes: a44810123f9e ("dm: core: Add dev_read_resource() to read device resources") Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
2021-04-29net: phy: xilinx: Break while loop over ethernet phyMichal Simek1-2/+2
The commit 6c993815bbea ("net: phy: xilinx: Be compatible with live OF tree") change driver behavior to while loop which wasn't correct because the driver was looping over again and again. The reason was that ofnode_valid() is taking 0 as correct value. Fix it by changing while loop to ofnode_for_each_subnode() which is only loop over available nodes. Fixes: 6c993815bbea ("net: phy: xilinx: Be compatible with live OF tree") Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-04-29arm: a37xx: pci: Fix processing PIO transfersPali Rohár1-14/+28
Trying to clear PIO_START register when it is non-zero (which indicates that previous PIO transfer has not finished yet) causes an External Abort with SError 0xbf000002. This bug is currently worked around in TF-A by handling External Aborts in EL3 and ignoring this particular SError. This workaround was also discussed at: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=3c7dcdac5c50 https://lore.kernel.org/linux-pci/20190316161243.29517-1-repk@triplefau.lt/ https://lore.kernel.org/linux-pci/971be151d24312cc533989a64bd454b4@www.loen.fr/ https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/1541 Implement a proper fix to prevent this External Abort. As it is not possible to cancel a pending PIO transfer, simply do not start a new one if previous has not finished yet. In this case return an error to the caller. In most cases this SError happens when there is no PCIe card connected or when PCIe link is down. The reason is that in these cases a PIO transfer takes about 1.44 seconds. For this reason we also increase the wait timeout in pcie_advk_wait_pio() to 1.5 seconds. If PIO read transfer for PCI_VENDOR_ID register times out, or if it isn't possible to read it yet because previous transfer is not finished, return Completion Retry Status value instead of failing, to give the caller a chance to send a new read request. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2021-04-29phy: marvell: utmi: update utmi config which fixes usb2.0 instabilityGrzegorz Jaszczyk2-5/+27
- Add additional step which enables the Impedance and PLL calibration. - Enable old squelch detector instead of the new analog squelch detector circuit and update host disconnect threshold value. - Update LS TX driver strength coarse and fine adjustment values. Change-Id: Ifa0a585bfb5ecab0bfa033eed6874ff98b16a7df Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
2021-04-29phy: marvell: add support for SFI1Igal Liberman2-7/+9
In CP115, comphy4 can be configured into SFI port1 (in addition to SFI0). This patch adds the option described above. In addition, rename all existing SFI/XFI references: COMPHY_TYPE_SFI --> COMPHY_TYPE_SFI0 No functional change for exsiting configuration. Change-Id: If9176222e0080424ba67347fe4d320215b1ba0c0 Signed-off-by: Igal Liberman <igall@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2021-04-29phy: marvell: fix pll initialization for second utmi portGrzegorz Jaszczyk2-13/+32
According to Design Reference Specification the PHY PLL and Calibration register from PHY0 are shared for multi-port PHY. PLL control registers inside other PHY channels are not used. This commit reworks utmi device tree nodes in a way that common PHY PLL registers are moved to main utmi node. Accordingly both child nodes utmi-unit range is reduced and register offsets in utmi_phy.h are updated to this change. This fixes issues in scenarios when only utmi port1 was in use, which resulted with lack of correct pll initialization. Change-Id: Icc520dfa719f43a09493ab31f671efbe88872097 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
2021-04-29phy: marvell: allow to initialize up to 6 USB portsGrzegorz Jaszczyk1-1/+1
New products can contain up to 6 usb ports, therefore allow to initialize all relevant UTMI PHYs. Change-Id: I28c36e59fa0e3e338bb3ee0cee2240b923f39785 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-by: Kostya Porotchkin <Kostya.Porotchkin@cavium.com>
2021-04-29phy: marvell: cp110: mark u-boot power-off callsIgal Liberman1-2/+2
It helps ATF to determine who called power off function (U-boot/Linux) and act accordingly Change-Id: Icfc5cbfdba64754496812154272b28c0ff639f0f Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-by: Grzegorz Jaszczyk <jaz@semihalf.com>
2021-04-29phy: marvell: fix handling of unconnected comphyChristine Gharzuzi1-0/+4
- the default value of comphy pipe selector is set to PCIe (x4) in case of unconnected comphy the default value remains 0x4 which may lead to several issues with comphy initialization. - this patch adds SMC call that powers off the comphy lane in case of unconnected comphy. Change-Id: I196b2916518dd8df3b159ffa85e2989b8e483087 Signed-off-by: Christine Gharzuzi <chrisg@marvell.com> Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-by: Grzegorz Jaszczyk <jaz@semihalf.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-21 00:26:55 +0300