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2021-06-18net: e1000: do not attempt to set hwaddr for i210 without FLASHTim Harvey2-0/+5
commit f1bcad22dd19 ("net: e1000: add support for writing to EEPROM") adds support for storing hwaddr in EEPROM however i210 devices do not support this and thus results in errors such as: Warning: e1000#0 failed to set MAC address' Check if a flash device is present and if not return -ENOSYS indicating this is not supported. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-06-18Fix a memory leak issue in the RX port initialization.Hou Zhiqiang1-1/+3
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-06-18clk: cosmetic change in uclassPatrick Delaunay1-1/+1
Remove the tab in clk_get_bulk to respect the coding rules. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-06-18dfu: add error callbackPatrick Delaunay1-0/+12
Add error callback in dfu stack to manage some board specific behavior on DFU targets. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-06-18dfu: dfu_mtd: set max_buf_size to erasesize also for NOR devicesPatrick Delaunay1-4/+1
For NOR devices the logical DFU buffer size is the sector_size, as it is done in dfu_sf.c or in spi/sf_mtd.c (sf_mtd_info.erasesize = flash->sector_size) For NAND the DFU size was already limited to erasesize as has_pages = true. So the mtd dfu backend can use this erasesize for all the MTD devices, NOR and NAND with dfu->max_buf_size = mtd->erasesize This difference was initially copied from MTD command, where data is fully available in RAM without size limitation. This patch avoids to have many sector write in dfu_mtd.c at the end of the DFU transfer and avoids issues with USB timeout or WATCHDOG. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-06-18spi: stm32_qspi: Fix short data write operationDaniil Stas1-14/+15
TCF flag only means that all data was sent to FIFO. To check if the data was sent out of FIFO we should also wait for the BUSY flag to be cleared. Otherwise there is a race condition which can lead to inability to write short (one byte long) data. Signed-off-by: Daniil Stas <daniil.stas@posteo.net> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-06-18mtd: nand: NFC drivers for RK3308, RK2928 and othersYifeng Zhao3-0/+1270
This driver supports Rockchip NFC (NAND Flash Controller) found on RK3308, RK2928, RKPX30, RV1108 and other SOCs. The driver has been tested using 8-bit NAND interface on the ARM based RK3308 platform. Support Rockchip SoCs and NFC versions: - PX30 and RK3326(NFCv900). ECC: 16/40/60/70 bits/1KB. CLOCK: ahb and nfc. - RK3308 and RV1108(NFCv800). ECC: 16 bits/1KB. CLOCK: ahb and nfc. - RK3036 and RK3128(NFCv622). ECC: 16/24/40/60 bits/1KB. CLOCK: ahb and nfc. - RK3066, RK3188 and RK2928(NFCv600). ECC: 16/24/40/60 bits/1KB. CLOCK: ahb. Supported features: - Read full page data by DMA. - Support HW ECC(one step is 1KB). - Support 2 - 32K page size. - Support 8 CS(depend on SoCs) Limitations: - No support for the ecc step size is 512. - Untested on some SoCs. - No support for subpages. - No support for the builtin randomizer. - The original bad block mask is not supported. It is recommended to use the BBT(bad block table). Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-06-18pci: pcie_dw_rockchip: Replace msleep occurences by udelayAnand Moon1-5/+5
Replace msleep occurences by udelay. drivers/pci/pcie_dw_rockchip.c:254:3: warning: implicit declaration of function 'msleep' [-Wimplicit-function-declaration] Cc: Patrick Wildt <patrick@blueri.se> Cc: Neil Armstrong <narmstrong@baylibre.com> Cc: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Anand Moon <linux.amoon@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-06-18pci: pcie_dw_rockchip: Drop the unused variable warningAnand Moon1-2/+0
Drop the unused variable warning below. drivers/pci/pcie_dw_rockchip.c:161:6: warning: unused variable 'val' [-Wunused-variable] 161 | u32 val; | ^~~ Cc: Patrick Wildt <patrick@blueri.se> Cc: Neil Armstrong <narmstrong@baylibre.com> Cc: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Patrick Wildt <patrick@blueri.se> Signed-off-by: Anand Moon <linux.amoon@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-06-18pci: pcie_dw_rockchip: Fixed the below compilation errorAnand Moon1-2/+2
Use the generic error number instead of specific error number. Changes fix the below error. drivers/pci/pcie_dw_rockchip.c: In function 'rk_pcie_read': drivers/pci/pcie_dw_rockchip.c:70:10: error: 'PCIBIOS_UNSUPPORTED' undeclared (first use in this function) 70 | return PCIBIOS_UNSUPPORTED; | ^~~~~~~~~~~~~~~~~~~ drivers/pci/pcie_dw_rockchip.c: In function 'rk_pcie_write': drivers/pci/pcie_dw_rockchip.c:90:10: error: 'PCIBIOS_UNSUPPORTED' undeclared (first use in this function) 90 | return PCIBIOS_UNSUPPORTED; | ^~~~~~~~~~~~~~~~~~~ Cc: Patrick Wildt <patrick@blueri.se> Cc: Neil Armstrong <narmstrong@baylibre.com> Cc: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Patrick Wildt <patrick@blueri.se> Signed-off-by: Anand Moon <linux.amoon@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-06-18rockchip: rk3568: Add sdram driverJoseph Chen2-0/+57
Add the driver for rk3568 u-boot to get sdram capacity. Signed-off-by: Joseph Chen <chenjh@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-06-18rockchip: rk3568: add clock driverElaine Zhang2-0/+2960
Add rk3568 clock driver and cru structure definition. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-06-17Merge tag 'u-boot-atmel-2021.10-a' of ↵Tom Rini1-19/+18
https://source.denx.de/u-boot/custodians/u-boot-atmel into next First set of u-boot-atmel features for the 2021.10 cycle: This feature set converts the boards pm9261 and pm9263 Ethernet support to DM; enables hash command for all SAM boards; fixes the NAND pmecc bit-flips correction; adds Falcon boot for sama5d3_xplained board; and other minor adjustments.
2021-06-17Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqTom Rini7-13/+91
- fsl-qoriq: Bug fixes related pfe, eth, thermal node, vid.c, cpu release, mmc, usb, env, etc for Layerscape boards - powerpc: Update Maintainers for some boards.
2021-06-17net: tsec: add option to set device max-speed via dtsAleksandar Gerasimovski1-1/+6
Current tsec adapter sets adapter gigabit capabilities by default, and in reality this must not always be the case. It is possible that tsec adapter is used for 100Mbps connection, and in this case setting 1000Mbps capabilities can lead to some side effects such longer autoneg process. In our ls102x designs this problem leads to long autoneg times (> 4 sec) in case board rgmii link is 100Mbps capable only. Limiting the rgmii link capabilities provides faster and smoother link establishment. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-06-17mmc: fsl_esdhc_imx: drop CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33Yangbo Lu1-6/+1
There is no i.MX board using such option. Drop it. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-06-17mmc: fsl_esdhc: convert to CONFIG_FSL_ESDHC_VS33_NOT_SUPPORTYangbo Lu2-3/+21
For eSDHC, power supply is through peripheral circuit. Some eSDHC versions have value 0 of the bit but that does not reflect the truth. 3.3V is common for SD/MMC, and is supported for all boards with eSDHC in current u-boot. So, make 3.3V is supported in default in code. CONFIG_FSL_ESDHC_VS33_NOT_SUPPORT can be enabled if future board does not support 3.3V. This is also a fix-up for one previous patch, which converted to use IS_ENABLED() for CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 that is not a Kconfig option. Fixes: 52faec31827e ("mmc: fsl_esdhc: replace most #ifdefs by IS_ENABLED()") Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-06-17pci: layerscape-ep: Add check of the PCIe controller enablementHou Zhiqiang1-0/+4
Stop to initialize the PCIe controller if it's disabled by RCW. Fixes: 118e58e26eba ("pci: layerscape: Split the EP and RC driver") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-06-17armv8: ls1012a: Pass PPFE firmware to Linux through FDTChaitanya Sakinam1-2/+58
Read Linux PPFE firmware from flash partition and pass it to Linux through FDT entry. So that we can avoid placing PPFE firmware in Linux rootfs. (FDT may increase at max by 64KB) Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com> Signed-off-by: Anji J <anji.jagarlmudi@nxp.com> Signed-off-by: Biwen Li <biwen.li@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-06-17clk: k210: Move k210 clock out of its own subdirectorySean Anderson5-15/+14
Now that we have only one clock driver, we don't need to have our own subdirectory. Move the driver back with the rest of the clock drivers. The MAINTAINERS for kendryte pinctrl is also fixed since it has always been wrong. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-06-17clk: k210: Remove bypass driverSean Anderson2-274/+1
This driver no longer serves a purpose now that we have moved away from CCF. Drop it. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-06-17clk: k210: Don't set PLL rates if we are already at the correct rateSean Anderson1-7/+8
This speeds up boot by preventing multiple reconfigurations of the PLLs. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-06-17clk: k210: Re-add support for setting rateSean Anderson1-5/+84
This adds support for setting clock rates, which was left out of the initial CCF expunging. There are several tricky bits here, mostly related to the PLLS: * The PLL's bypass is broken. If the PLL is reconfigured, any child clocks will be stopped. * PLL0 is the parent of ACLK which is the CPU and SRAM's clock. To prevent stopping the CPU while we configure PLL0's rate, ACLK is reparented to IN0 while PLL0 is disabled. * PLL1 is the parent of the AISRAM clock. This clock cannot be reparented, so we instead just disallow changing PLL1's rate after relocation (when we are using the AISRAM). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-06-17clk: k210: Implement soc_clk_dumpSean Anderson1-2/+66
Since we are no longer using CCF we cannot use the default soc_clk_dump. Instead, implement our own. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-06-17clk: k210: Move pll into the rest of the driverSean Anderson3-594/+601
Now that there no separate PLL driver, we can no longer make the PLL functions static. By moving the PLL driver in with the rest of the clock code, we can make these functions static again. We still keep the pll header for unit testing, but it is pretty reduced. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-06-17clk: k210: Rewrite to remove CCFSean Anderson3-523/+439
This is effectively a complete rewrite to remove all dependency on CCF. The code is now smaller, and so is the binary. It also takes up less memory at runtime (since we don't have to create 40 udevices). In general, I am much happier with this driver as much of the complexity and late binding has been removed. The k210_*_params structs which were previously used to initialize CCF clocks are now used as the complete configuration. Since we can write our own division logic, we can now do away with several "half" clocks which only existed to provide constant factors of two. The clock IDs have been renumbered to remove unused clocks. This may not be the last time they are renumbered, since we have diverged with Linux. There are also still a few clocks left out which may need to be added back in. In general, I have tried to leave out behavioral changes. However, there is a small bugfix regarding ACLK. According to the technical reference manual, its mux comes *after* its divider (which is present only for PLL0). This would have required yet another intermediate clock to fix with CCF, but with the new driver it is just 2 lines of code :) Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-06-17clk: Allow force setting clock defaults before relocationSean Anderson4-13/+20
Since 291da96b8e ("clk: Allow clock defaults to be set during re-reloc state for SPL only") it has been impossible to set clock defaults before relocation. This is annoying on boards without SPL, since there is no way to set clock defaults before U-Boot proper. In particular, the aisram rate must be changed before relocation on the K210, since U-Boot will hang if we try and change the rate while we are using aisram. To get around this, extend the stage parameter to allow force setting defaults, even if they would be otherwise postponed for later. A device tree property was decided against because of the concerns in the original commit thread about the overhead of repeatedly parsing the device tree. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-06-16Merge tag 'u-boot-imx-20210616' of ↵Tom Rini7-16/+213
https://gitlab.denx.de/u-boot/custodians/u-boot-imx u-boot-imx-20210616 ------------------- - imxrt : fixes, USB, imxrt1020-evk - imx8m: fix for verdin-imx8mm Add conga-QMX8 board - imx6 : documentation for pico-imx6: Add SeeedStudio NPI-IMX6ULL Support ventana: DM PCI - imx7d: added SMEGW01 board CI : https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/7765
2021-06-16ls1012a: net: pfe: remove pfe stop from bootcmdMian Yousaf Kaukab1-1/+1
When using bootefi to boot a EFI binary, u-boot is supposed to provide networking service for EFI application. Currently, 'pfe stop' command is called from bootcmd before running bootefi. As a result network stops working for EFI applications and console is flooded with "Rx pkt not on expected port" messages. Implement board_quiesce_devices() for ls1012a boards and call pfe_command_stop() from it instead of calling 'pfe stop' from *_bootcmd and bootcmd. Tested-by: Anji Jagarlmudi <anji.jagarlmudi@nxp.com> Signed-off-by: Mian Yousaf Kaukab <ykaukab@suse.de> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> [Fixed checkpatch space error] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-06-11dma: ti: k3-udma: Add support for native configuration of chan/flowVignesh Raghavendra2-4/+215
In absence of Device Manager (DM) services such as at R5 SPL stage, driver will have to natively setup TCHAN/RCHAN/RFLOW cfg registers. Add support for the same. Note that we still need to send chan/flow cfg message to TIFS via TISCI client driver in order to open up firewalls around chan/flow but setting up of cfg registers is handled locally. U-Boot specific code is in a separate file included in main driver so as to maintain similarity with kernel driver in order to ease porting of code in future. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210607141753.28796-8-vigneshr@ti.com
2021-06-11soc: ti: k3-navss-ringacc: Add support for native configuration of ringsVignesh Raghavendra2-3/+94
In absence of Device Manager (DM) services such as at R5 SPL stage, driver will have to natively setup Ring Cfg registers. Add support for the same. Note that we still need to send RING_CFG message to TIFS via TISCI client driver in order to open up firewalls around Rings. U-Boot specific code is in a separate file included in main driver so as to maintain similarity with kernel driver in order to ease porting of code in future. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210607141753.28796-7-vigneshr@ti.com
2021-06-11firmware: ti_sci: Add support for Resoure Management at R5 SPL stage.Vignesh Raghavendra1-10/+81
On J721e and J7200, MCU R5 core (boot master) itself would run Device Manager (DM) Firmware and interact with TI Foundational Security (TIFS) firmware to enable DMA and such other Resource Management (RM) services. So, during R5 SPL stage there is no such RM service available and ti_sci driver will have to directly interact with TIFS using DM to DMSC channels to request RM resources. Therefore add DT binding and driver for the same. This driver will handle Resource Management services at R5 SPL stage. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210607141753.28796-4-vigneshr@ti.com
2021-06-11firmware: ti_sci: Implement GET_RANGE with static dataVignesh Raghavendra2-0/+128
In case of R5 SPL, GET_RANGE API service is not available (as DM services are not yet up), therefore service such calls locally using per SoC static data. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210607141753.28796-3-vigneshr@ti.com
2021-06-11mailbox: k3-sec-proxy: Add DM to DMSC communication threadVignesh Raghavendra1-1/+1
R5 SPL would need to talk to DMSC using DM to DMSC sec-proxy threads. Mark these as valid threads in the driver. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210607141753.28796-2-vigneshr@ti.com
2021-06-11Merge tag 'xilinx-for-v2021.07-rc5' of ↵Tom Rini1-1/+17
https://source.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2021.07-rc5 zynqmp: - Fix ANALOG_BUS value after powerup - Disable EFI_CAPSULE_ON_DISK_EARLY zynqmp-gqspi: - Fix write issue
2021-06-11cmd: ti: pd: Add debug command for K3 power domainsTero Kristo1-3/+3
Add support command for debugging K3 power domains. This is useful with the HSM rearch setup, where power domains are directly controlled by SPL instead of going through the TI SCI layer. The debugging support is only available in the u-boot codebase though, so the raw register access power domain layer must be enabled on u-boot side for this to work. By default, u-boot side uses the TI SCI layer, and R5 SPL only uses the direct access methods. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-06-11power: domain: Introduce driver for raw TI K3 PDsTero Kristo3-0/+376
Normally, power domains are handled via TI-SCI in K3 SoCs. However, SPL is not going to have access to sysfw resources, so it must control them directly. Add driver for supporting this. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-06-11clk: add support for TI K3 SoC clocksTero Kristo3-0/+387
Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11clk: add support for TI K3 SoC PLLTero Kristo3-0/+296
Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11clk: fix set_rate to clean up cached rates for the hierarchyTero Kristo1-0/+19
Clock rates are cached within the individual clock nodes, and right now if one changes a clock rate somewhere in the middle of the tree, none of its child clocks notice the change. To fix this, clear up all the cached rates for us and our child clocks. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11clk: fix assigned-clocks to pass with deferring providerTero Kristo1-0/+18
If a clock provider is not ready for assigning default rates/parents during its probe, it may return -EPROBE_DEFER directly from xlate. Handle this special case properly by skipping the entry and adjusting the return value to pass. The defaults will be handled properly in post probe phase then. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11clk: sci-clk: fix return value of set_rateTero Kristo1-2/+4
Set rate should return the new clock rate on success, and negative error value on failure. Fix this, as currently set_rate returns 0 on success. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11clk: do not attempt to fetch clock pointer with null deviceTero Kristo1-0/+2
Bail out early if device returned for the parent clock is null. This avoids warning prints like this when doing clk dump: dev_get_uclass_priv: null device Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11clk: fixed_rate: add API for directly registering fixed rate clocksTero Kristo1-0/+45
Current driver only supports registering fixed rate clocks from DT. Add new API which makes it possible to register fixed rate clocks directly from e.g. platform specific clock drivers. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11remoteproc: k3-r5: remove sysfw PM calls if not supportedTero Kristo1-11/+19
With the sysfw rearch, sysfw PM calls are no longer available from SPL level. To properly support this, remove the is_on checks and the reset assertion from the R5 remoteproc driver as these are not supported. Attempting to access unavailable services will cause the device to hang. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11spi: zynqmp_gqspi: Fix write issueAshok Reddy Soma1-1/+17
Enable manual start in zynqmp_qspi_fill_gen_fifo(). Also enable GQSPI_IXR_GFNFULL_MASK and check for it instead of GQSPI_IXR_GFEMTY_MASK. Add dummy write to genfifo register in chipselect. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
2021-06-09rtc: davinci: fix date loaded on resetDario Binacchi1-0/+10
On reset, the RTC loads the 2000-01-01 date with a wrong day of the week (Sunday instead of Saturday). Signed-off-by: Dario Binacchi <dariobin@libero.it> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210602203805.11494-9-dariobin@libero.it
2021-06-09rtc: davinci: add driver model supportDario Binacchi1-61/+367
Update the driver to support the device tree and the driver model. The read / write helpers in rtc_ops allow access to scratch registers only. The offset parameter is added to the address of the scratch0 register. Support for non-DM has been removed as there were no users. Signed-off-by: Dario Binacchi <dariobin@libero.it> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210602203805.11494-8-dariobin@libero.it
2021-06-09rtc: davinci: use unlock/lock mechanismDario Binacchi1-0/+14
The RTC module contains a kicker mechanism to prevent any spurious writes from changing the register values. To set the time, you must first unlock the TC registers, update them and then lock. Signed-off-by: Dario Binacchi <dariobin@libero.it> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210602203805.11494-6-dariobin@libero.it
2021-06-09rtc: davinci: check BUSY bit before set TC registersDario Binacchi1-9/+36
To write correct data to the TC registers, the STATUS register must be read until the BUSY bit is equal to zero. Once the BUSY flag is zero, there is a 15 μs access period in which the TC registers can be programmed. The rtc_wait_not_busy() has been inspired by the Kernel. Signed-off-by: Dario Binacchi <dariobin@libero.it> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210602203805.11494-5-dariobin@libero.it
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