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2019-10-29mmc: fsl_esdhc: remove redundant DM_MMC checkingYangbo Lu1-2/+0
Remove redundant DM_MMC checking which is already in DM_MMC conditional compile block. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2019-10-29mmc: fsl_esdhc: make BLK as hard requirement of DM_MMCYangbo Lu1-32/+1
U-boot prefers DM_MMC + BLK for MMC. Now eSDHC driver has already support it, so let's force to use it. - Drop non-BLK support for DM_MMC introduced by below patch. 66fa035 mmc: fsl_esdhc: fix probe issue without CONFIG_BLK enabled - Support only DM_MMC + BLK (assuming BLK is always enabled for DM_MMC). - Use DM_MMC instead of BLK for conditional compile. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2019-10-27fdt: Fix alignment issue when reading 64-bits properties from fdtJean-Jacques Hiblot1-1/+1
The FDT specification [0] gives a requirement of aligning properties on 32-bits. Make sure that the compiler is aware of this constraint when accessing 64-bits properties. [0]: https://github.com/devicetree-org/devicetree-specification/blob/master/source/flattened-format.rst Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-10-27dm: core: Update log method for uclass_find_device_by_seqKever Yang1-4/+7
Use log() insted of debug() for uclass_find_device_by_seq function, since this print is very much and we can filter it out with log() interface. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Move #define to top of file as per docs: Signed-off-by: Simon Glass <sjg@chromium.org>
2019-10-27dm: regmap: Fix mask in regmap_update_bits()Simon Glass1-1/+1
This function assumes that the 'val' parameter has no masked bits set. This is not defined by the function prototype though. Fix the function to mask the value and update the documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-26Merge tag 'mips-pull-2019-10-25' of git://git.denx.de/u-boot-mipsTom Rini26-436/+1812
- bmips: add BCRM NAND support for BCM6368, BCM6328, BCM6362 and BCM63268 SoCs - bmips: various small fixes - mtmips: add new drivers for clock, reset-controller and pinctrl - mtmips: add support for high speed UART - mtmips: update/enhance drivers for SPI and ethernet - mtmips: add support for MMC
2019-10-26Merge branch '2019-10-24-ti-imports'Tom Rini23-12/+32384
- Enable DFU on dra7xx boards - Further Keystone 3 platform improvements
2019-10-26ram: k3-j721e: Add support for J721E DDR controllerKevin Scholz21-0/+32102
The J721E DDR subsystem comprises DDR controller, DDR PHY and wrapper logic to integrate these blocks in the device. The DDR subsystem is used to provide an interface to external SDRAM devices which can be utilized for storing program or data. Introduce support for the DDR controller and DDR phy within the DDR subsystem. Signed-off-by: Kevin Scholz <k-scholz@ti.com Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-26ram: k3-am654: Do not rely on default values for certain DDR registerJames Doublesin2-7/+58
Added the following registers to the DDR configuration: - ACIOCR0, - ACIOCR3, - V2H_CTL_REG, - DX8SLxDQSCTL. Modified enable_dqs_pd and disable_dqs_pd to only touch the associated bit fields for pullup and pulldown registers (to preserve slew rate and other bits in that same register). Also update the dts files in the same patch to maintain git bisectability. Signed-off-by: James Doublesin <doublesin@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-26ram: k3-am654: add support for LPDDR4 and DDR3L DDRsJames Doublesin1-11/+230
Added training support for LPDDR4 and DDR3L DDRs. Also added/changed some register configuration to support all 3 DDR types Signed-off-by: James Doublesin <doublesin@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-25Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini22-1538/+282
- DWC3 improvements - i.MX7 EHCI bugfix
2019-10-25Merge tag 'u-boot-atmel-2020.01-b' of ↵Tom Rini3-0/+74
https://gitlab.denx.de/u-boot/custodians/u-boot-atmel Second set of u-boot-atmel features and fixes for 2020.01 cycle This feature set includes Eugen's work on a new tiny flexcom driver and eeprom mac retrieval for the sam9x60-ek board.
2019-10-25Merge tag 'xilinx-for-v2020.01-part2' of ↵Tom Rini9-25/+104
https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze Xilinx/FPGA changes for v2020.01 part 2 common: - Fix manual relocation for repeatable commands arm: - Also clean up generated dtbos microblaze: - Add support for Manual relocation in crypto framework - Tune and align architecture bootm support zynq: - DT sync ups - Some defconfig updates - Remove empty board_early_init_f() zynqmp: - Clean firmware handing via drivers/firmware/ - DT/defconfig name alignments - DT cleanups with using firmware based clock driver - Some defconfig updates - Add IIO ina226 DT description - Tune zynqmp_psu_init_minimalize.sh script - Add single nand mini configuration, e-a2197, m-a2197-02/03 and zcu216 versal: - Clean firmware handing via drivers/firmware/ - Add gpio support - Enable DT overlay/USB/CLK/FPGA - DT updates - Tune mini configuration spi: - gqspi - Remove unused headers
2019-10-25mmc: mtk-sd: add a dts property cd-active-high for builtin-cd modeWeijie Gao1-1/+5
This patch adds a dts property cd-active-high for builtin-cd mode to make it configurable instead of using hardcoded active-low. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25mmc: mtk-sd: add support for MediaTek MT7620/MT7628 SoCsWeijie Gao2-4/+21
This patch adds mmc support for MediaTek MT7620/MT7628 SoCs. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25net: mt7628-eth: add support to isolate LAN/WAN portsWeijie Gao1-0/+32
This patch add support for mt7628-eth to isolate LAN/WAN ports mainly to prevent LAN devices from getting IP address from WAN. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25net: mt7628-eth: free rx descriptor on receiving failureWeijie Gao1-0/+3
When received a packet with an invalid length recorded in rx descriptor, we should free this rx descriptor to allow us to continue to receive following packets. Without doing so, u-boot will stuck in a dead loop trying to process this invalid rx descriptor. This patch adds a call to mt7628_eth_free_pkt() after received an invalid packet length. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25net: mt7628-eth: make phy link up detection optional via DTWeijie Gao2-29/+31
The mt7628 has an embedded ethernet switch (5 phy ports + 1 cpu port). Although in IOT mode only port0 is usable, the phy0 is still connected to the switch, not the ethernet gmac directly. This patch rewrites it and makes it optional. It can be turned on by adding mediatek,poll-link-phy = <?> explicitly into the eth node. By default the driver is switch mode with all 5 phy ports working without link detection. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25net: mt7628-eth: remove hardcoded gpio settings and regmap-based phy resetWeijie Gao1-37/+8
This patch removes hardcoded gpio settings as they have been replaced by pinctrl in dts, and also replaces regmap-based phy reset with a more generic reset controller. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25phy: mt76x8-usb-phy: add slew rate calibration and remove non-mt7628 partWeijie Gao2-68/+158
This patch adds slew rate calibration for mt76x8-usb-phy, removes code which belongs to mt7620, and gets rid of using syscon and regmap by using clock driver and reset controller. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25reset: add reset controller driver for MediaTek MIPS platformWeijie Gao3-0/+90
This patch adds reset controller driver for MediaTek MIPS platform and header file for mt7628. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25pinctrl: add support for MediaTek MT7628Weijie Gao7-0/+747
This patch adds pinctrl support for mt7628, with a file for common pinmux functions and a file for mt7628 which has additional support for pinconf. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25spi: mt7621-spi: restore default register value after each xferWeijie Gao1-13/+17
Currently this driver uses a different way to implement the spi xfer, by modifying some fields of two registers, which is incompatible with the MTK's original SDK linux driver. This will cause the flash data being damaged by the SDK driver. This patch lets the mt7621_spi_set_cs() restore the original register fields after cs deactivated. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25spi: mt7621-spi: remove data cache and rewrite its xfer functionWeijie Gao1-106/+91
The mt7621 spi controller supports continuous generic half-duplex spi transaction. There is no need to cache xfer data at all. To achieve this goal, the OPADDR register must be used as the first data to be sent. And follows the eight generic DIDO registers. But one thing different between OPADDR and DIDO registers is OPADDR has a reversed byte order. With this patch, any amount of data can be read/written in a single xfer function call. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25spi: mt7621-spi: use clock frequency from clk driverWeijie Gao1-7/+13
This patch lets the spi driver to use clock provided by the clk driver since the new clk-mt7628 driver provides accurate sys clock frequency. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25clk: add clock driver for MediaTek MT76x8 platformWeijie Gao3-0/+162
This patch adds a clock driver for MediaTek MT7628/7688 SoC. It provides clock gate control as well as getting clock frequency for CPU/SYS/XTAL and some peripherals. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25serial: serial_mtk: add non-DM version for SPLWeijie Gao2-17/+187
This patch adds non-DM version for mtk hsuart driver and makes it compatible with ns16550a driver in configuration. This is needed in SPL with CONFIG_SPL_DM disabled for reducing size. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25serial: serial_mtk: enable FIFO and disable flow controlWeijie Gao1-0/+21
This patch adds codes to enable FIFO and disable flow control taken from ns16550 driver. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25drivers: nand: brcmnand: fix nand_chip ecc layout structureWilliam Zhang1-156/+104
The current brcmnand driver is based on 4.18 linux kernel which uses mtd_set_ooblayout to set ecc layout. But nand base code in u-boot is from old kernel which does not use this new API and expect nand_chip.ecc.layout structure to be set. This cause nand_scan_tail function running into a bug check if the device has a different oob size than the default ones. This patch ports the brcmstb_choose_ecc_layout function from kernel 4.6.7 that supports the ecc layout struture and replaces the mtd_set_ooblayout method Signed-off-by: William Zhang <william.zhang@broadcom.com> Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-10-25nand: brcm: add BCM6368 supportÁlvaro Fernández Rojas3-0/+124
This adds support for BCM6368, BCM6328, BCM6362 and BCM63268 SoCs. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-10-24spi-nor-ids: Add support for Adesto AT25SL321Fabio Estevam1-0/+1
Add an entry for the Adesto AT25SL321 SPI NOR chip. This SPI NOR chip is found in the Embedded Artist i.MX7ULP COM board. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-24mtd: spi: Clean up usage of CONFIG_SPI_FLASH_MTDFrieder Schrempf3-5/+5
Most boards currently use SPI_FLASH_MTD only in U-Boot proper, not in SPL. They often rely on hacks in the board header files to include this option conditionally. To be able to fix this, we previously introduced a separate option SPL_SPI_FLASH_MTD. Therefore we can now adjust the Makefile and change the code in sf_probe.c and sf_internal.h to use CONFIG_IS_ENABLED(SPI_FLASH_MTD). We also need to move all occurences of CONFIG_SPI_FLASH_MTD from the header files to the according defconfigs. The affected boards are socfpga, aristainetos, cm_fx6, display5, ventana, rcar-gen2, dh_imx6 and da850evm. We do this all in one patch to guarantee bisectibility. This change was tested with buildman to make sure it does not introduce any regressions by comparing the resulting binary sizes. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-24spi-nor: spi-nor-ids: Add USE_FSR flag for mt25q* and n25q* entryVignesh Raghavendra1-5/+6
n25q* and mt25q* (both 256Mb and 512Mb) flashes support Flag status register that indicates various errors that may be encountered during erase/write operations. Therefore add USE_FSR flag wherever missing. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-24spi-nor: spi-nor-ids: Add entries for mt25q variantsVignesh Raghavendra1-0/+3
mt25q* flashes support stateless 4 byte addressing opcodes. Add entries for the same. These flashes have bit 6 set in 5th byte of READ ID response when compared to n25q* variants. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-24spi-nor: spi-nor-ids: Disable SPI_NOR_4B_OPCODES for n25q512* and n25q256*Vignesh Raghavendra1-4/+4
Per datasheets of n25q256* and n25q512* not all variants of n25q256* and n25q512* support 4 Byte stateless addressing opcodes. Therefore drop SPI_NOR_4B_OPCODES flag from these entries Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-24spi: designware_spi: Disable and free clock when remove driverLey Foon Tan1-1/+15
Disable and free clock when remove driver. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-24mtd: spi-nor-core: Replace MTD_SPI_NOR_USE_4K_SECTORS with ↵Vignesh Raghavendra2-2/+2
SPI_FLASH_USE_4K_SECTORS U-Boot uses CONFIG_SPI_FLASH_USE_4K_SECTORS to enable 4K small sector support. Use that instead of MTD_SPI_NOR_USE_4K_SECTORS. Reported-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-24mtd: spi-nor-core: Use dev_err for reporting erase/write failuresVignesh Raghavendra1-3/+3
Use dev_err() when reporting reason for erase/write failures so that users can be made aware of the reason for failure. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-24mtd: spi: Add a new option SPL_SPI_FLASH_MTD to KconfigFrieder Schrempf1-0/+8
To allow SPI_FLASH_MTD being enabled separately in SPL we add a new option. The only user currently is the stm32mp15_basic board. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Acked-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-24spi: Kconfig: Enable SPI_SUNXI for SUNXIJagan Teki1-0/+1
SPI_SUNXI driver is fully dm-aware and the Allwinner architecture kconfig would have logic to enable the DM_SPI. So, select default spi sunxi driver for sunxi architecture. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-24mtd: spi: Kconfig: Imply SPI_FLASH if DM_SPI_FLASHJagan Teki1-0/+1
DM_SPI_FLASH should require spi flash interface code for dm version, so imply SPI_FLASH core by default if any board enabled DM_SPI_FLASH. This overcome the explicit enablement of CONFIG_SPI_FLASH on respective boards when DM_SPI_FLASH being used. Acked-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-24dm: spi: Change cs_info op to return -EINVAL for invalid cs numBin Meng5-5/+5
We need distinguish the following two situations in various SPI APIs: - given chip select num is invalid - given chip select num is valid, but no device is attached Currently -ENODEV is returned for both cases. For the first case, it's more reasonable to return -EINVAL instead of -ENODEV for invalid chip select numbers. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # SoPine Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-24dm: spi: Return 0 if driver does not implement ops->cs_infoBin Meng1-4/+3
If an SPI controller driver does not implement ops->cs_info, that probably means any chip select number could be valid, hence let's return 0 for spi_cs_info(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # SoPine Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-24spi: Kconfig: Add help textJagan Teki1-0/+17
Add detailed help text for SPI support. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-24mtd: spi-nor: ids: Add is25wp256 chipJagan Teki1-0/+2
Add is25wp256, chip to spi-nor id table. Tested on SiFive FU540 board. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-24mtd: spi: Kconfig: Update CONFIG_SPI_FLASHJagan Teki1-3/+2
1) CONFIG_SPI_FLASH is not just a legacy code, but it has common core code which handle both dm and non-dm spi flash code. So fix the info text to make it clear globally. 2) Since it's flash core it shouldn't depends on legacy SPI, so remove the 'depends on SPI' Cc: Vignesh R <vigneshr@ti.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-24Merge branch '2019-10-24-UFS-support'Tom Rini11-59/+3455
- Add Universal Flash Storage (UFS) support
2019-10-24ehci-mx6: Update EHCI driver to support OTG0 on i.MX7ULPYe Li2-16/+43
The ULP has two USB controllers. These two controllers have similar NC registers layout as i.MX7D. But OTG0 uses UTMI PHY simliar as i.MX6, not the integrated PHY on i.MX7D. The OTG1 needs off-chip HSIC PHY or ULPI PHY to work. This patch only supports OTG0 with UTMI PHY. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Fabio Estevam <festevam@gmail.com>
2019-10-24usb: ehci-mx6: Fix bus enumeration for iMX7 SoCsIgor Opaniuk1-7/+8
This fixes the issues with calculation of controller indexes in ehci_usb_bind() for iMX7, as USB controllers on iMX7 SoCs aren't placed next to each other, and their addresses incremented by 0x10000. Example of USB nodes for iMX7S/D: usbotg1: usb@30b10000 { compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; reg = <0x30b10000 0x200>; ^^^^^^^^^^ .... usbotg2: usb@30b20000 { compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; reg = <0x30b20000 0x200>; ^^^^^^^^^^ .... usbh: usb@30b30000 { compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; reg = <0x30b30000 0x200>; ^^^^^^^^^^ .... Which was leading to usb enumeration issues: Colibri iMX7 # usb start starting USB... Bus usb@30b10000: USB EHCI 1.00 Bus usb@30b20000: probe failed, error -22 scanning bus usb@30b10000 for devices... 1 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found Fixes: 501547cec1("usb: ehci-mx6: Fix bus enumeration for DM case") Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2019-10-24arm64: zynqmp: Switch to xlnx-zynqmp-clk headerMichal Simek1-1/+0
Use prepared header instead of hardcoded values. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
generated by cgit v1.2.3 (git 2.39.0) at 2026-10-01 11:54:09 +0300