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2021-02-26ddr: marvell: a38x: fix write leveling suplementary algoMoti Buskila1-1/+4
commit ce62bef8fac559e27245259882e45f19cdc293ad upstream. - fix JIRA A7K8K-5056 - remove TEST_PATTERN write at the load patern stage earlier to WL SUP stage - the WL SUP stage already writes this pattern to the memory, if the pattern exist at the memory then the algorithm will fail, since it think that there are no phase to correct Signed-off-by: Moti Buskila <motib@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Signed-off-by: Marek Behún <marek.behun@nic.cz> Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2021-02-26pci: pci_mvebu: set local dev to number 1Marek Behún1-1/+1
Linux displays the real PCIe card connected to a mvebu PCIe slot as device 0, not 1. This is done by setting local dev number to 1, so that the local "Marvell Memory controller" device is on address 1. Let's do it also in U-Boot. With this commit the pci command in U-Boot prints something like: => pci Scanning PCI devices on bus 0 BusDevFun VendorId DeviceId Device Class Sub-Class _____________________________________________________________ 00.00.00 0x168c 0x003c Network controller 0x80 Signed-off-by: Marek Behún <marek.behun@nic.cz> Cc: Stefan Roese <sr@denx.de> Cc: Phil Sutter <phil@nwl.cc> Cc: Mario Six <mario.six@gdsys.cc> Cc: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de>
2021-02-26pci: pci_mvebu: refactor validation of addresses for config accessMarek Behún1-28/+31
Refactor validation of bdf parameter in mvebu_pcie_read/write_config functions. We can simplify the code by putting the validation into separate function. Also there are always only two devices visible on local bus: * on slot configured by function mvebu_pcie_set_local_dev_nr() (by default this register is set to 0) there is a "Marvell Memory controller", which isn't useful in root complex mode, * on all other slots the real PCIe card connected to the PCIe slot. We can simplify the code even more by simply allowing access only to the real PCIe card. Signed-off-by: Marek Behún <marek.behun@nic.cz> Cc: Stefan Roese <sr@denx.de> Cc: Phil Sutter <phil@nwl.cc> Cc: Mario Six <mario.six@gdsys.cc> Cc: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de>
2021-02-26pci: pci_mvebu: debug rd/wr config as other drivers doMarek Behún1-2/+2
Other drivers (aardvark, intel_fpga) print "(addr,size,val)" when debugging is enabled. Print size for pci_mvebu as well. Signed-off-by: Marek Behún <marek.behun@nic.cz> Cc: Stefan Roese <sr@denx.de> Cc: Phil Sutter <phil@nwl.cc> Cc: Mario Six <mario.six@gdsys.cc> Cc: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de>
2021-02-26pci: pci_mvebu: cosmetic fixMarek Behún1-3/+6
Write bdf address in a same way in mvebu_pcie_read/write_config. Signed-off-by: Marek Behún <marek.behun@nic.cz> Cc: Stefan Roese <sr@denx.de> Cc: Phil Sutter <phil@nwl.cc> Cc: Mario Six <mario.six@gdsys.cc> Cc: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de>
2021-02-26pci: pci_mvebu: use dev_seq instead of static variableMarek Behún1-3/+1
PCI uclass maps PCI bus numbers to the seq member of struct udevice. Use dev_seq(dev) as the bus number in mvebu_pcie_probe instead of an incrementing a static variable. Signed-off-by: Marek Behún <marek.behun@nic.cz> Cc: Stefan Roese <sr@denx.de> Cc: Phil Sutter <phil@nwl.cc> Cc: Mario Six <mario.six@gdsys.cc> Cc: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de>
2021-02-26arm: a37xx: pci: Set Max Payload Size and Max Read Request Size to 512 bytesPali Rohár1-0/+8
Fix usage of VL805 XHCI PCIe controller when it is connected via PCIe to Armada 3720 SOC. Without this U-Boot crashes when trying to access enumerated USB devices connected to this XHCI PCIe controller. This should be done according to the PCIe Link Initialization sequence, as defined in Marvell Armada 3720 Functional Specification. Linux has this code too. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2021-02-26mtd: spi-nor-ids: Add support of flash protection to w25q128Su Baocheng1-1/+4
The NOR flash w25q128 denoted by JEDEC ID 0xef4018 actually represents various models. From Winbond's website, I could only find 3 types of them: W25Q128JV-IQ/JQ datasheet:https://www.winbond.com/resource-files/ w25q128jv%20revg%2004082019%20plus.pdf W25Q128FV (SPI Mode) datasheet: https://www.winbond.com/resource-files/ w25q128fv%20rev.m%2005132016%20kms.pdf W25Q128BV datesheet: https://www.winbond.com/resource-files/ w25q128bv_revh_100313_wo_automotive.pdf According to the datasheets, all of these 3 types support BP(0,1,2) and TB bits in the status register (SR), so it could reuse the flash protection logic for ST Micro. So it should be safe to add the SPI_NOR_HAS_LOCK and SPI_NOR_HAS_TB flags to the w25q128 entry of spi_nor_ids table. Signed-off-by: Su Baocheng <baocheng.su@siemens.com> [jagan: remove comments in spi-nor-ids.c] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-02-26mtd: spi-nor-ids: Add Gigadevice GD25LQ64CAlper Nebi Yasak1-0/+5
Add GD25LQ24C 64Mbit chip to spi-nor id table. This chip is used on rk3399-gru-kevin: => sf probe SF: Detected gd25lq64c with page size 256 Bytes, erase size 4 KiB, total 8 MiB => sf erase 0x600000 0x200000 SF: 2097152 bytes @ 0x600000 Erased: OK => sf test 0x700000 0x1000 SPI flash test: 0 erase: 52 ticks, 76 KiB/s 0.608 Mbps 1 check: 5 ticks, 800 KiB/s 6.400 Mbps 2 write: 14 ticks, 285 KiB/s 2.280 Mbps 3 read: 3 ticks, 1333 KiB/s 10.664 Mbps Test passed 0 erase: 52 ticks, 76 KiB/s 0.608 Mbps 1 check: 5 ticks, 800 KiB/s 6.400 Mbps 2 write: 14 ticks, 285 KiB/s 2.280 Mbps 3 read: 3 ticks, 1333 KiB/s 10.664 Mbps The values are the same as in Linux, except adjusted for the U-Boot definition of INFO(). Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-02-26spi: imx: Implement set_speedMarek Vasut1-1/+4
The set_speed() callback should configure the bus speed, make it so. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-02-25net: cortina_ni: buffer overrunHeinrich Schuchardt1-1/+1
When copying to a u32 field we should use sizeof(u32) and not sizeof(*u32) in memcpy. On 64bit systems like cortina_presidio-asic-emmc_defconfig using sizeof(*u32) leads to a buffer overrun. Fixes: febe13b438b3 ("net: cortina_ni: Add eth support for Cortina Access CAxxxx SoCs") Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-By: Ramon Fried <rfried.dev@gmail.com>
2021-02-25mtd: rawnand: cortina_nand: missing initializationHeinrich Schuchardt1-1/+1
ca_do_bch_correction() takes a random value from the stack and starts counting bitflips from this value. Initialize the counter. This passed unnoticed as the value is finally ignored in the call hierarchy. Fixes: 161df94b3c43 ("mtd: rawnand: cortina_nand: Add Cortina CAxxxx SoC support") Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-02-25dm: ddr: socfpga: don't assign values that are not usedHeinrich Schuchardt1-7/+0
The values of left_edge[0] and right_edge[0] are overwritten before they are used. Remove the superfluous assignments. Fixes: 285b3cb939a8 ("dm: ddr: socfpga: fix gen5 ddr driver to not use bss") Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-02-25rng: iProc rng200: Rename ..._platdata variables to just ..._platPeter Robinson1-10/+10
In 8a8d24bd Simon dropped data from all the various _platdata calls but it seems this wasn't caught for the RNG200 driver from when it was posted to merged. This fixes that issue. Fixes: 537f0018 (rng: Add iProc RNG200 driver) Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
2021-02-25virtio: fix off by one device id comparisonVincent Stehlé1-1/+1
VIRTIO_ID_MAX_NUM is the largest device ID plus 1. Therefore a device id cannot be greater or equal to VIRTIO_ID_MAX_NUM. Fix the comparison accordingly. Fixes: 8fb49b4c7a82 ("dm: Add a new uclass driver for VirtIO transport devices") Signed-off-by: Vincent Stehlé <vincent.stehle@laposte.net> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
2021-02-23Merge tag 'xilinx-for-v2021.04-rc3' of ↵Tom Rini12-126/+200
https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2021.04-rc3 qspi: - Support for dual/quad mode - Fix speed handling clk: - Add clock enable function for zynq/zynqmp/versal gem: - Enable clock for Versal - Fix error path - Fix mdio deregistration path fpga: - Fix buffer alignment for ZynqMP xilinx: - Fix reset reason clearing in ZynqMP - Show silicon version in SPL for Zynq/ZynqMP - Fix DTB selection for ZynqMP - Rename zc1275 to zcu1275 to match DT name
2021-02-23spi: zynqmp_gqspi: fix set_speed bug on multiple runsBrandon Maier1-12/+11
If zynqmp_qspi_set_speed() is called multiple times with the same speed, then on the second call it will skip recalculating the baud_rate_val as it assumes the speed is already configured correctly. But it will still write the baud_rate_val to the configuration register and call zynqmp_gqspi_set_tapdelay(). Because it skipped recalculating the baud_rate_val, it will use the initial value of 0 . This causes the driver to run at maximum speed which for many spi flashes is too fast and causes data corruption. Instead only write out a new baud_rate_val if we have calculated the correct baud_rate_val. This opens up another issue with the "if (speed == 0)", we don't save off the new plat->speed_hz value when setting the baud rate on the speed=0 path. Instead mimic what the Linux zynqmp gqspi driver does, and have speed==0 just use the same calculation as a normal speed. That will cause the baud_rate_val to use the slowest speed possible, which is the safest option. Signed-off-by: Brandon Maier <brandon.maier@rockwellcollins.com> CC: jagan@amarulasolutions.com CC: michal.simek@xilinx.com CC: Ashok Reddy Soma <ashokred@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-02-23net: gem: Fix error path in zynq_gem_probeMichal Simek1-4/+4
Clean up error path in connection where priv->rxbuffers and priv->tx_bd are allocated. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-02-23net: gem: Enable ethernet rx clock for versalT Karthik Reddy1-6/+27
Enable rx clock along with tx clock for versal platform. Use compatible data to enable/disable clocks in the driver. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-02-23i2c: i2c_cdns: Enable i2c clockT Karthik Reddy1-0/+7
Enable i2c controller clock from driver probe function by calling clk_enable(). Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2021-02-23clk: versal: Add support to enable clocksT Karthik Reddy1-0/+11
Add clock enable functionality in versal clock driver to enable clocks from peripheral drivers using clk_ops. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-02-23clk: zynqmp: Add support to enable clocksT Karthik Reddy1-0/+49
Add clock enable functionality in zynqmp clock driver to enable clocks from peripheral drivers using clk_ops. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-02-23clk: zynq: Add dummy clock enable functionMichal Simek8-9/+18
A lot of Xilinx drivers are checking -ENOSYS which means that clock driver doesn't have enable function. Remove this checking from drivers and create dummy enable function as was done for clk_fixed_rate driver by commit 6bf6d81c1112 ("clk: fixed_rate: add dummy enable() function"). Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-02-23fpga: zynqpl: fix buffer alignmentMichael Walle1-1/+1
Due to pointer arithmetic, "sizeof(u32) * ARCH_DMA_MINALIGN" is subtracted. It seems that the original intention was to just subtract ARCH_DMA_MINALIGN. Fix it. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-02-23serial: s5p: Allow independent selectionMark Kettenis2-1/+8
Currently support for the Samsung serial port driver is part of CONFIG_S5P which controls selection of several drivers for the S5P family. Give it its own config option such that we can use it on other SoCs as well. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Patrick Wildt <patrick@blueri.se> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2021-02-23power: pmic: remove pmic_max8997/8 filesJaehoon Chung3-141/+0
Remove pmic_max8997/8 files about no-DM. There are already existed max8997/8 as driver-model. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2021-02-22Merge tag 'u-boot-amlogic-20210222' of ↵Tom Rini4-0/+176
https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic - adds adc-keys button driver - fix meson-saradc driver to get reference voltage - add adc-keys test for sandbox - enable adc-keys for VIM3 & VIM3L boards - fix button.h build
2021-02-22Merge tag 'ti-v2021.04-rc3' of ↵Tom Rini1-2/+2
https://gitlab.denx.de/u-boot/custodians/u-boot-ti - Fix ethernet on J721e - Sync am335x DT nodes from Linux 5.9-rc7 - Minor Clock fixes
2021-02-22Merge tag 'video-for-v2021.04-rc3' of ↵Tom Rini6-490/+213
https://gitlab.denx.de/u-boot/custodians/u-boot-video - splash_source warning fix when building with 64-bit toolchains - lq123p1jx31 and nv101wxmn51 compatible in simple panel driver - remove not used mb862xx driver - add Himax HX8238D panel driver - s/video_uc_platdata/video_uc_plat/
2021-02-22clk: ti: improve debug messages for clkctrl driverDario Binacchi1-2/+2
The previous version printed the same debug message for both the enable and disable routines without highlighting whether you were enabling or disabling the module. It is now clear whether you are enabling or disabling the module. Signed-off-by: Dario Binacchi <dariobin@libero.it>
2021-02-22uec.h: fix COFIG_DM typoRasmus Villemoes1-1/+1
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: Heiko Schocher <hs@denx.de>
2021-02-22dm_qe_uec.c: fix indentation in uec_set_mac_if_mode()Rasmus Villemoes1-2/+2
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: Heiko Schocher <hs@denx.de>
2021-02-21Merge tag 'for-v2021.04' of https://gitlab.denx.de/u-boot/custodians/u-boot-i2cTom Rini24-81/+109
i2c changes for v2021.04 new feature: - Allow disabling driver model for I2C in SPL fixes: - i2c-gpio: Fix GPIO output - at91: fix crash when using 'i2c probe'
2021-02-21dm: i2c: use CONFIG_IS_ENABLED macro for DM_I2C/DM_I2C_GPIOIgor Opaniuk19-71/+71
Use CONFIG_IS_ENABLED() macro, which provides more convenient way to check $(SPL)DM_I2C/$(SPL)DM_I2C_GPIO configs for both SPL and U-Boot proper. CONFIG_IS_ENABLED(DM_I2C) expands to: - 1 if CONFIG_SPL_BUILD is undefined and CONFIG_DM_I2C is set to 'y', - 1 if CONFIG_SPL_BUILD is defined and CONFIG_SPL_DM_I2C is set to 'y', - 0 otherwise. All occurences were replaced automatically using these bash cmds: $ find . -type f -exec sed -i 's/ifndef CONFIG_DM_I2C/if !CONFIG_IS_ENABLED(DM_I2C)/g' {} + $ find . -type f -exec sed -i 's/ifdef CONFIG_DM_I2C/if CONFIG_IS_ENABLED(DM_I2C)/g' {} + $ find . -type f -exec sed -i 's/defined(CONFIG_DM_I2C)/CONFIG_IS_ENABLED(DM_I2C)/g' {} + $ find . -type f -exec sed -i 's/ifndef CONFIG_DM_I2C_GPIO/if !CONFIG_IS_ENABLED(DM_I2C_GPIO)/g' {} + $ find . -type f -exec sed -i 's/ifdef CONFIG_DM_I2C_GPIO/if CONFIG_IS_ENABLED(DM_I2C_GPIO)/g' {} + $ find . -type f -exec sed -i 's/defined(CONFIG_DM_I2C_GPIO)/CONFIG_IS_ENABLED(DM_I2C_GPIO)/g' {} + Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-21dm: i2c: allow disabling driver model in SPLIgor Opaniuk3-3/+24
At present if U-Boot proper uses driver model for I2C, then SPL has to also. While this is desirable, it places a significant barrier to moving to driver model in some cases. For example, with a space-constrained SPL it may be necessary to enable CONFIG_SPL_OF_PLATDATA which involves adjusting some drivers. This patch introduces a separate Kconfig symbols for enabling DM_I2C and DM_I2C_GPIO support in SPL. This will also help to get away from dirty workarounds to achieve non-DM I2C support for SPL, which is currently used in some board header files like: ifdef CONFIG_SPL_BUILD undef CONFIG_DM_I2C endif Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io> Reviewed-by: Tom Rini <trini@konsulko.com>
2021-02-21i2c: at91: fix crash when using 'i2c probe'Eugen Hristev1-0/+4
When issuing 'i2c probe', the driver was crashing, because at probe there is a request with zero length buffer to write to i2c bus. The xfer_msg function assumes the buffer is always there, and never checks for the buffer length. => i2c dev 0 Setting bus to 0 => i2c probe Valid chip addresses: data abort pc : [<7ffa97dc>] lr : [<7ffa96f8>] reloc pc : [<66f277dc>] lr : [<66f276f8>] sp : 7fb7c110 ip : 7ff87a28 fp : 7ff99938 r10: 00000002 r9 : 7fb7dec0 r8 : 00000000 r7 : e181c600 r6 : 7fb88c20 r5 : 00000000 r4 : 7fb7c128 r3 : 00000000 r2 : 00000001 r1 : 00000000 r0 : 00000009 Flags: nZCv IRQs off FIQs off Mode SVC_32 Code: eb0092f4 e1a00005 e8bd81f0 e594300c (e5d33000) Resetting CPU ... Fixes: 8800e0fa20 ("i2c: atmel: add i2c driver") Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2021-02-21i2c: i2c-gpio: Fix GPIO outputHarm Berntsen1-7/+10
The dm_gpio_set_dir_flags function cannot be used to update the configuration of a GPIO pin because it does a bitwise OR with the existing flags. Looks like commit 788ea834124b ("gpio: add function _dm_gpio_set_dir_flags") has introduced this behaviour and the i2c-gpio driver has been broken since. Signed-off-by: Harm Berntsen <harm.berntsen@nedap.com> CC: Heiko Schocher <hs@denx.de> CC: Patrick Delaunay <patrick.delaunay@st.com>
2021-02-21pci: renesas: Fix BAR mapping on Gen3Marek Vasut1-3/+3
Because the first PCIExAR(n) register is configured with the mapping, It is the second PCIExAR(n) register that must be written with 0, not the last one. Update the n from 4 to 1 to select the correct register. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2021-02-21pci: renesas: Make map address and mask power of two on Gen3Marek Vasut1-3/+6
Both the map address and mask must be power of two per documentation, adjust the code accordingly. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2021-02-21pci: renesas: Add root bus handling on Gen3Marek Vasut1-1/+14
Add code to access the PCIe root bus space and configure it. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2021-02-20drivers: video: Add Support for Himax HX8238D PanelMoses Christopher3-0/+208
* SPI based initialization for HX8238D * Resolution: 320x240 * Color-Mode: RGB * Initial Work is done by Sjoerd Simons https://gitlab.apertis.org/packaging/u-boot/-/blob\ /5f259720e3e64965d50da89a841ad6eb256a47df/debian/patches\ /apertis/powertools/0005-video-Add-Himax-HX8238-D-driver.patch * Tested on Bosch Guardian Board Cc: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: Moses Christopher <BollavarapuMoses.Christopher@in.bosch.com>
2021-02-20Replace video_uc_platdata with video_uc_platDario Binacchi2-3/+3
The video_uc_platdata structure no longer exists. It has been renamed video_uc_plat. Signed-off-by: Dario Binacchi <dariobin@libero.it>
2021-02-20video: eliminate unused drivers/video/mb862xx.cHeinrich Schuchardt2-487/+0
The mb862xx driver does not conform to the driver model and is unused. Eliminate it. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-02-20video: simple_panel: Add boe,nv101wxmn51 displayAlper Nebi Yasak1-0/+1
Add "boe,nv101wxmn51" to the compatible node. This is the panel for chromebook_bob. Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-02-20video: simple_panel: Add sharp,lq123p1jx31 displayAlper Nebi Yasak1-0/+1
Add "sharp,lq123p1jx31" to the compatible node. This is the panel for chromebook_kevin. Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-02-19mmc: rockchip_dw_mmc: use mmc_pwrseq instead of rockchip_mmc_pwrseqJaehoon Chung1-39/+3
Use mmc_pwrseq instead of rockchip_mmc_pwrseq. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-02-19mmc: meson_gx_mmc: use mmc_pwrseq instead of meson_mmc_pwrseqJaehoon Chung1-42/+3
Use mmc_pwrseq instead of meson_mmc_pwrseq. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com>
2021-02-19mmc: pwrseq: add mmc-pwrseq file to provide a generic interfaceJaehoon Chung3-0/+59
Add mmc-pwrseq file to provide a generic interface. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-02-19mmc: mmc_spi: Document the 3 local functionsBin Meng1-1/+35
mmc_spi_sendcmd(), mmc_spi_readdata() and mmc_spi_writedata() are currently undocumented. Add comment blocks to explain the arguments and the return value. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-02-19mmc: mmc_spi: Fix potential spec violation in receiving card responseBin Meng1-15/+17
After command is sent and before card response shows up on the line, there is a variable number of clock cycles in between called Ncr. The spec [1] says the minimum is 1 byte and the maximum is 8 bytes. Current logic in mmc_spi_sendcmd() has a flaw that it could only work with certain SD cards with their Ncr being just 1 byte. When resp_match is false, the codes try to receive only 1 byte from the SD card. On the other hand when resp_match is true, the logic happens to be no problem as it loops until timeout to receive as many bytes as possible to see a match of the expected resp_match_value. However not every call to mmc_spi_sendcmd() is made with resp_match being true hence this exposes a potential issue with SD cards that have a larger Ncr value. Given no issue was reported as of today, we can reasonably conclude that all cards being used on the supported boards happen to have a 1 byte Ncr timing requirement. But a broken case can be triggered by utilizing QEMU to emulate a larger value of Ncr (by default 1 byte Ncr is used on QEMU). This commit fixes such potential spec violation to improve the card compatibility. [1] "Physical Layer Specification Version 8.00" chapter 7.5.1: Command / Response chapter 7.5.4: Timing Values Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
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