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2020-12-18mtd: spinand: Do not erase the block before writing a bad block markerFrieder Schrempf1-9/+0
Currently when marking a block, we use spinand_erase_op() to erase the block before writing the marker to the OOB area. Doing so without waiting for the operation to finish can lead to the marking failing silently and no bad block marker being written to the flash. In fact we don't need to do an erase at all before writing the BBM. The ECC is disabled for raw accesses to the OOB data and we don't need to work around any issues with chips reporting ECC errors as it is known to be the case for raw NAND. Fixes: 7529df465248 ("mtd: nand: Add core infrastructure to support SPI NANDs") Cc: stable@vger.kernel.org Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200218100432.32433-4-frieder.schrempf@kontron.de
2020-12-18mtd: spinand: Explicitly use MTD_OPS_RAW to write the bad block marker to OOBFrieder Schrempf1-0/+1
When writing the bad block marker to the OOB area the access mode should be set to MTD_OPS_RAW as it is done for reading the marker. Currently this only works because req.mode is initialized to MTD_OPS_PLACE_OOB (0) and spinand_write_to_cache_op() checks for req.mode != MTD_OPS_AUTO_OOB. Fix this by explicitly setting req.mode to MTD_OPS_RAW. Fixes: 7529df465248 ("mtd: nand: Add core infrastructure to support SPI NANDs") Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200218100432.32433-3-frieder.schrempf@kontron.de
2020-12-18mtd: spinand: Stop using spinand->oobbuf for buffering bad block markersFrieder Schrempf1-7/+7
For reading and writing the bad block markers, spinand->oobbuf is currently used as a buffer for the marker bytes. During the underlying read and write operations to actually get/set the content of the OOB area, the content of spinand->oobbuf is reused and changed by accessing it through spinand->oobbuf and/or spinand->databuf. This is a flaw in the original design of the SPI NAND core and at the latest from 13c15e07eedf ("mtd: spinand: Handle the case where PROGRAM LOAD does not reset the cache") on, it results in not having the bad block marker written at all, as the spinand->oobbuf is cleared to 0xff after setting the marker bytes to zero. To fix it, we now just store the two bytes for the marker on the stack and let the read/write operations copy it from/to the page buffer later. Fixes: 7529df465248 ("mtd: nand: Add core infrastructure to support SPI NANDs") Cc: stable@vger.kernel.org Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200218100432.32433-2-frieder.schrempf@kontron.de
2020-12-18mtd: spi-nor-ids: Add SECT_4K to mx25l12805dRobert Marko1-1/+1
According to the mx25l12805d datasheet it supports using 4K or 64K sectors. So lets add the SECT_4K to enable 4K sector usage. Datasheet: https://www.mxic.com.tw/Lists/Datasheet/Attachments/7321/MX25L12805D,%203V,%20128Mb,%20v1.2.pdf Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-12-18mtd: spi-nor-ids: Add Winbond W25M512JW flash entryBiju Das1-0/+1
Add Winbond W25M512JW flash device description. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-12-18mtd: spi-nor-ids: Add Winbond W25M512JV flash entryLad Prabhakar1-0/+1
Add Winbond W25M512JV flash device description. Linux already has the flash entry present. A snippet below: { "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024...}, Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-12-18spi: migrate trace to dev and log macro in spi uclassPatrick Delaunay1-23/+28
Define LOG_CATEGORY and change printf and pr_* to dev_ (when dev is available) or log_ macro. This patch adds the support of logging feature with log command (filtering, display of device name in trace) and allows to suppress traces via the syslog driver. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-12-17Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini3-7/+42
- r8152, xhci fixes
2020-12-16eth/r8152: fix the aggregation issueHayes Wang2-2/+20
Remove the redundant setting for USB_RX_EARLY_SIZE. Besides, for RTL8153B, it is necessary to notify the hardware of the changes of the aggregation settings. Signed-off-by: Hayes Wang <hayeswang@realtek.com>
2020-12-16eth/r8152: free previous memory if r8152_eth_probe failHayes Wang1-2/+7
The r8152_eth_probe() may allocate a memory for ss->dev_priv. It has to be freed if r8152_eth_probe() fails finally. Signed-off-by: Hayes Wang <hayeswang@realtek.com>
2020-12-16usb: xhci: fix lack of short packet event trb handlingRan Wang1-3/+15
For bulk IN transfer, the codes will set ISP flag to request event TRB being generated by xHC for the case of short packet. So when encountering buffer-cross-64K-boundary (which we will divide payload and enqueuqe more than 1 transfer TRB), and the first TRB ends up with a short packet condition it will trigger an short packet code transfer event per that flag and cause more than 1 event TRB generated for this transfer. However, current codes will only handle the first transfer event TRB then mark current transfer completed, causing next transfer failure due to event TRB mis-match. Such issue has been observed on some Layerscape platforms (LS1028A, LS1088A, etc) with USB ethernet device. This patch adds a loop to make sure the event TRB for last transfer TRB has been handled in time. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-12-16x86: edison: Use dwc3-generic driver for Intel EdisonAndy Shevchenko1-0/+1
Use generic Synopsys DesignWare 3 driver on Intel Edison. For now it's just a stub which allows future refactoring. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-12-14pinctrl: meson: fix bit manipulation of pin bias configurationNeil Armstrong1-2/+2
This fixes the wrong usage of clrsetbits_le32(), badly setting the set argument. Fixes: c4c726c26b ("pinctrl: meson: add pinconf support") Reported-by: Anton Arapov <arapov@gmail.com> Reported-by: Otto Meier <gf435@gmx.net> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-12-14usb: dwc3-meson-g12a: always configure dr-modeMarek Szyprowski1-3/+0
dwc3_meson_g12a_force_mode() sets the dr-mode of the USB PHY. However it skips setting the mode if it matches the one done during driver probe (stored in private structure). This fails if the mode has been changed to other value and then back to initial one. Fix this by configuring the dr-mode always, regadless of the one set at the driver probe). This fixes operation of USB gadget based drivers when they are initialized for the second time. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-12-14dm: treewide: Rename ..._platdata variables to just ..._platSimon Glass250-1151/+1145
Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-14dm: treewide: Update 'auto' declarations to be on one lineSimon Glass9-18/+9
Fix up the code style for those declarations that should now fit onto one line, which is all of them that currently do not. This is needed for dtoc to detect the structs correctly, at present. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-14dm: treewide: Rename ofdata_to_platdata() to of_to_plat()Simon Glass335-708/+709
This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-14dm: treewide: Rename dev_get_platdata() to dev_get_plat()Simon Glass308-947/+947
Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-14dm: Rename 'platdata_size' to 'plat_size'Simon Glass1-8/+7
Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-14dm: treewide: Rename 'platdata' variables to just 'plat'Simon Glass468-1278/+1267
We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: treewide: Rename auto_alloc_size members to be shorterSimon Glass910-1255/+1251
This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: core: Drop unused parameter from dm_extended_scan_fdt()Simon Glass1-3/+3
This doesn't need to be passed the devicetree anymore. Drop it. Also rename the function to drop the _fdt suffix. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: core: Drop unused parameter from dm_scan_fdt()Simon Glass1-5/+4
This doesn't need to be passed the devicetree anymore. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: core: Combine the flattree and livetree binding codeSimon Glass1-58/+16
At present there are two copies of this code. With ofnode we can combine them to reduce duplication. Update the dm_scan_fdt_node() function and adjust its callers. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: core: Add an ofnode function to get the devicetree rootSimon Glass1-6/+2
This is needed in at least one place. Avoid the conditional code in root.c by adding this inline function. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: core: Drop device_bind_offset()Simon Glass1-8/+0
This function is not needed since the standard device_bind() can be used instead. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: Drop uses of dev_set_of_offset()Simon Glass6-13/+6
The need for this can be avoided by passing the correct node to the device_bind() function. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: Remove uses of device_bind_offset()Simon Glass17-45/+42
This function is not needed since the standard device_bind() can be used instead. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: core: Add a livetree function to check node statusSimon Glass1-0/+10
Add a way to find out if a node is enabled or not, based on its 'status' property. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: core: Rename device_bind_ofnode() to device_bind()Simon Glass8-16/+16
This is the standard function to use when binding devices. Drop the '_ofnode' suffix to make this clear. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: core: Rename device_bind() to device_bind_offset()Simon Glass17-31/+33
This function is not necessary anymore, since device_bind_ofnode() does the same thing and works with both flattree and livetree. Rename it to indicate that it is special. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13sandbox: serial: Update to use membuffSimon Glass1-29/+19
Rather than implementing our own circular queue, use membuff. This allows us to read multiple bytes at once into the serial input. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13sandbox: serial: Convert to livetreeSimon Glass1-3/+1
Use a livetree function to read the colour. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13serial: sandbox: Drop unnecessary #ifdefsSimon Glass1-9/+2
CONFIG_OF_CONTROL is always enabled for sandbox (as it should be for all boards), so we can drop it. Also use IS_ENABLED() for the SPL check. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-11Merge tag 'u-boot-atmel-fixes-2021.01-b' of ↵Tom Rini2-5/+3
https://gitlab.denx.de/u-boot/custodians/u-boot-atmel Second set of u-boot-atmel fixes for 2021.01 cycle This set includes very important fixes for: MMC booting on several boards, drive strength on sam9x60ek mmc lines, compile issues for timer.c old driver, removal of unwanted access to sam9x60 bit for oscillator bypass mode, and eeproms read on sama5d2_icp.
2020-12-10net: pfe_eth: read PFE ESBC header flash with spi_flash_read APIBiwen Li1-4/+44
Read PFE ESBC header flash with spi_flash_read API - logs as follows, Net: SF: Detected s25fs512s with page size 256 Bytes, erase size 256 KiB, total 64 MiB "Synchronous Abort" handler, esr 0x96000210 elr: 000000008206db44 lr : 0000000082004ea0 (reloc) elr: 00000000b7ba6b44 lr : 00000000b7b3dea0 x0 : 00000000b79407e8 x1 : 0000000040640000 x2 : 0000000000000050 x3 : 0000000000000000 x4 : 000000000000000a x5 : 0000000000000050 x6 : 0000000000000366 x7 : 00000000b7942308 x8 : 00000000b76407c0 x9 : 0000000000000008 x10: 0000000000000044 x11: 00000000b7634d1c x12: 000000000000004f x13: 0000000000000044 x14: 00000000b7634d98 x15: 00000000b76407c0 x16: 0000000000000000 x17: 0000000000000000 x18: 00000000b7636dd8 x19: 0000000000000000 x20: 00000000b79407d0 x21: 00000000b79407e8 x22: 0000000040640000 x23: 00000000b7634e58 x24: 0000000000000000 x25: 0000000003800000 x26: 00000000b7bdd000 x27: 0000000000000000 x28: 0000000000000000 x29: 00000000b7634d10 Code: d2800003 eb03005f 54000101 d65f03c0 (f8636826) Resetting CPU ... Signed-off-by: Biwen Li <biwen.li@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-12-10pci: layerscape: fix a dead loop issueHou Zhiqiang1-0/+2
Fixes: commit 8ec619f8fd84 ("pci: layerscape: Fixup PCIe EP mode DT nodes for LX2160A rev2") This added the PCIe EP nodes fixup of LX2160A, but it didn't update the condition value when there isn't a property 'apio-wins'. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> [Fixed checkpatch error] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-12-10armv8: lx2162a: Add Soc changes to support LX2162AMeenakshi Aggarwal6-7/+14
LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-12-10drivers/net/phy: Add CORTINA_NO_FW_UPLOAD to KconfigMeenakshi Aggarwal2-4/+13
Move CORTINA_NO_FW_UPLOAD to Kconfig file so that it can be controlled via defconfig files. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-12-10pci: ls_pcie_g4: Add size check for config resourceWasim Khan1-0/+8
resource "config" is required to have minimum 4KB space to access all config space of PCI Express EP. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-12-10pci: layerscape: Add size check for config resourceWasim Khan1-1/+7
resource "config" is required to have minimum 8KB space as per hardware documentation. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-12-10pci: ls_pcie_g4: Print pcie controller number starting from 1Wasim Khan1-4/+7
Print pcie controller number starting from 1 Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
2020-12-10pci: layerscape: Update print of pcie controllerWasim Khan2-3/+7
Print pcie controller number starting from 1 Signed-off-by: Wasim Khan <wasim.khan@nxp.com> [Trimmed subject] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-12-09Merge tag 'u-boot-stm32-20201209' of ↵Tom Rini14-14/+14
https://gitlab.denx.de/u-boot/custodians/u-boot-stm - Manage CONFIG_ENV_EXT4_DEVICE_AND_PART in stm32mp1 board - Update ARM STI and ARM STM STM32MP Arch maintainers emails - Enable internal pull-ups for SDMMC1 on DHCOM SoM
2020-12-09treewide: Update email address Patrick Delaunay and Patrice ChotardPatrice Chotard14-14/+14
Update Patrick and my email address with the one dedicated to upstream activities. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-12-07clk: at91: sam9x60: remove the parsing of atmel, main-osc-bypassClaudiu Beznea1-4/+1
Remove the parsing of atmel,main-osc-bypass DT property as the SAM9X60 have no support for crystal oscillator bypass. Setting this bit might affect the device functionality. Fixes: a64862284f65 ("clk: at91: sam9x60: add support compatible with CCF") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-12-06power: pmic: add SPL_DM_PMIC_PCA9450 symbol to KconfigIgor Opaniuk1-0/+7
Add SPL_DM_PMIC_PCA9450 symbol to Kconfig. Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-12-06pca9450a: fix i2c addressMax Krummenacher1-1/+1
The I2C address is 0x25, not 0x35. This according to the datasheet and tests with a PCA9450A. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-12-06mmc: fsl_esdhc_imx: optimize the timing settingHaibo Chen1-8/+24
For imx usdhc/esdhc, once set the DDR_EN, enable the DDR mode, the card clock will be divied by 2 automatically by the host. So need to first config the DDR_EN correctly, then update the card clock. This will make sure the actual card clock is as our expected. IC also suggest config the DDR_EN firstly, then config the clock divider. For HS400/HS400ES mode, need to config the strobe dll, this need to based on the correct target clock rate, so need to do this after clock rate is update. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-12-06mmc: fsl_esdhc_imx: add wait_dat0() supportHaibo Chen1-0/+15
Add wait_dat0() support, upper layer will use this callback. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
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