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path: root/drivers/net/phy
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2020-05-19common: Drop linux/bitops.h from common headerSimon Glass9-0/+9
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-19common: Drop linux/delay.h from common headerSimon Glass10-0/+10
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-19common: Drop log.h from common headerSimon Glass10-0/+10
Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-19command: Remove the cmd_tbl_t typedefSimon Glass2-6/+8
We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-19common: Drop net.h from common headerSimon Glass1-0/+1
Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-10net: phy: realtek: add rx delay support for RTL8211FFugang Duan1-0/+11
Add RX delay enable support for RTL8211F PHY. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Fugang Duan <fugang.duan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-07phy: atheros: consolidate {ar8031|ar8035}_config()Michael Walle1-27/+3
The two functions are now exactly the same, remove one of them. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2020-05-07phy: atheros: ar8035: remove static clock configMichael Walle1-13/+0
We can configure the clock output in the device tree. Disable the hardcoded one in here. This is highly board-specific and should have never been enabled in the PHY driver. If bisecting shows that this commit breaks your board it probably depends on the clock output of your Atheros AR8035 PHY. Please have a look at doc/device-tree-bindings/net/phy/atheros.txt. You need to set "clk-out-frequency = <125000000>" because that value was the hardcoded value until this commit. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2020-05-07phy: atheros: add device tree bindings and configMichael Walle1-2/+222
Add support for configuring the CLK_25M pin as well as the RGMII I/O voltage by the device tree. By default the AT803x PHYs outputs the 25MHz clock of the XTAL input. But this output can also be changed by software to other frequencies. This commit introduces a generic way to configure this output. Also the PHY supports different RGMII I/O voltages: 1.5V, 1.8V and 2.5V. An internal LDO is able to provide 1.5V (default) and 1.8V. The 2.5V option needs an external supply voltage. This commit adds support to switch the internal LDO to 1.8V. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2020-05-07phy: atheros: move delay config to common functionMichael Walle1-16/+22
Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2020-05-07phy: atheros: introduce debug read and write functionsMichael Walle1-16/+41
Provide functions to read and write the Atheros debug registers. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2020-05-07phy: atheros: use defines for PHY IDsMichael Walle1-3/+7
Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2020-05-07phy: atheros: fix AR8021 PHY ID maskMichael Walle1-1/+1
The upper bits are all the OUI. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2020-05-07phy: atheros: Clarify the intention of ar8021_configVladimir Oltean1-4/+4
Debug register 5 contains TX_CLK DELAY at bit 8 and reserved values at the other bit positions, just like the other PHYs in the family do. Therefore, it is not necessary to hardcode the reserved values, but instead simply follow the read-modify-write procedure from the common function. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2020-05-07phy: atheros: Explicitly disable RGMII delaysVladimir Oltean1-0/+8
To eliminate any doubts about the out-of-reset value of the PHY, that the driver previously relied on. If bisecting shows that this commit breaks your board you probably have a wrong PHY interface mode. You probably want the PHY_INTERFACE_MODE_RGMII_RXID or PHY_INTERFACE_MODE_RGMII_ID mode. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2020-05-07phy: atheros: Clarify the configuration of the CLK_25M output pinVladimir Oltean1-5/+14
Also take the opportunity to use the phy_read_mmd and phy_write_mmd convenience functions. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2020-05-07phy: atheros: Use common functions for RGMII internal delaysVladimir Oltean1-28/+41
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2020-05-07phy: atheros: Make RGMII Tx delays actually configurable for AR8035Vladimir Oltean1-4/+0
Delete the extraneous write to debug reg 5 that enables Tx delay When the driver was originally introduced in commit "6027384a phylib: Add Atheros AR8035 GETH PHY support", the Tx delay was being unconditionally enabled. Then during "2ec4d10b phy: atheros: add support for RGMII_ID, RGMII_TXID and RGMII_RXID", the author did not notice that code for enabling Tx delay code was already. Therefore, the if condition for Tx delay has always been useless for this PHY since this commit introduced it. Prior to this patch, every AR8035 PHY in U-boot had Tx delay enabled. After this patch, only those who define the interface as RGMII_TXID or RGMII_ID will. This is to be expected, but will nonetheless break the setups of those who didn't know they rely on Tx delay implicitly. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2020-05-01net: phy: micrel: Add basic support for KSZ9131Philippe Schenker1-0/+58
This adds basic support for the new Micrel KSZ9131 phy. Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
2020-05-01net: phy: micrel: Use defines for PHY_IDs and MASKPhilippe Schenker1-2/+2
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
2020-03-10net: phy: marvell: Unify 88E151x series phy_driverClemens Gruber1-55/+10
The PHY models of the Marvell 88E151x series are not reliably distinguishable by their uid / PHY identifiers. The 88E1510, 88E1512, 88E1514 and 88E1518 all have the same OUI and model number and bits 3:0 in the PHY Identifier 2 (Page 0, Reg 3) are described as HW revision number, but both 88E1510 and 88E1518 PHYs were observed with the same HW rev number (1). Before commit 83cfbeb0df9f ("net: phy: Fix mask so that we can identify Marvell 88E1518"), the 88E151x were detected because the HW revision bits were masked from the uid. After that change, 88E1510/12/18 were all detected as 88E1518 and the 88E1510 specific code was no longer run. I modified the mask to again ignore all four HW revision bits, removed the 88E1510 specific code (board-specific LED/INTn setup), which was not called since late 2016 anyway and renamed the config function and phy_driver struct to the better fitting 88e151x. The uid and mask bits 3:0 are now again the same as in the Linux kernel. Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com>
2020-03-10net: phy: dp83867: Add SGMII mode type switchingMichal Simek1-0/+12
This patch adds ability to switch beetween two PHY SGMII modes. Some hardware, for example, FPGA IP designs may use 6-wire mode which enables differential SGMII clock to MAC. Patch description, dt flags have been done in mainline Linux by commit a2111c460c0c ("net: phy: dp83867: Add documentation for SGMII mode type") and by commit 507ddd5c0d47 ("net: phy: dp83867: Add SGMII mode type switching") Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2020-03-10net: phy: Fix overlong PHY timeoutAndre Przywara1-1/+1
Commit 27c3f70f3b50 ("net: phy: Increase link up delay in genphy_update_link()") increased the per-iteration waiting time from 1ms to 50ms, without adjusting the timeout counter. This lead to the timeout increasing from the typical 4 seconds to over three minutes. Adjust the timeout counter evaluation by that factor of 50 to bring the timeout back to the intended value. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Fixes: net: phy: Increase link up delay in genphy_update_link() ("27c3f70f3b50") Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Matthias Brugger <mbrugger@suse.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2020-03-10drivers: net: phy: aquantia: make it less verboseAlex Marginean1-12/+12
The driver now unconditionally prints some information that's not universally useful. Replace printf with debug. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2020-03-10drivers: net: phy: aquantia: drop XGMII as a valid system interface protoAlex Marginean1-8/+9
Use either USXGMII or XFI in aquantia_set_proto and drop XGMII as a valid protocol configuration. The PHY doesn't support it, it's just used as an alias for one of the other two protocols. Signed-off-by: Florin Chiculita <florinlaurentiu.chiculita@nxp.com> Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2020-03-10phy: Include NC-SI in phy setupSamuel Mendoza-Jonas1-0/+9
Add NC-SI to the usual phy handling. This makes two notable changes: - Somewhat similar to a fixed phy, phy_connect() will create an NC-SI phy if CONFIG_PHY_NCSI is defined. - An early return is added to phy_read() and phy_write() to handle a case like the NC-SI phy which does not define a bus. Signed-off-by: Samuel Mendoza-Jonas <sam@mendozajonas.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2020-03-10phy: Add support for the NC-SI protocolSamuel Mendoza-Jonas3-0/+902
This introduces support for the NC-SI protocol, modelled as a phy driver for other ethernet drivers to consume. NC-SI (Network Controller Sideband Interface) is a protocol to manage a sideband connection to a proper network interface, for example a BMC (Baseboard Management Controller) sharing the NIC of the host system. Probing and configuration occurs by communicating with the "remote" NIC via NC-SI control frames (Ethernet header 0x88f8). This implementation is roughly based on the upstream Linux implementation[0], with a reduced feature set and an emphasis on getting a link up as fast as possible rather than probing the full possible topology of the bus. The current phy model relies on the network being "up", sending NC-SI command frames via net_send_packet() and receiving them from the net_loop() loop (added in a following patch). The ncsi-pkt.h header[1] is copied from the Linux kernel for consistent field definitions. [0]: https://github.com/torvalds/linux/tree/master/net/ncsi [1]: https://github.com/torvalds/linux/blob/master/net/ncsi/ncsi-pkt.h Signed-off-by: Samuel Mendoza-Jonas <sam@mendozajonas.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2020-02-28net: phy: dp83867: Clean force link good bitMichal Simek1-0/+4
On Xilinx ZynqMP revA board initial value of PHYCR register is 0x5448 which means FORCE_LINK_GOOD is already setup. Origin code was doing write but the new code is doing read/modify/write and keep this bit untouched. That's why ethernet stop to work. The patch is cleaning this bit when PHYCR value is composed. Tested on Xilinx zcu102-revA and zcu104-rev1.0 boards. Fixes: 37d6265f2bfa ("net: phy: dp83867: refactor rgmii configuration") Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
2020-02-06dm: core: Create a new header file for 'compat' featuresSimon Glass1-0/+1
At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-06dm: core: Require users of devres to include the headerSimon Glass1-0/+1
At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
2019-12-09drivers: net: aquantia: check system interface too when checking for link upAlex Marginean1-5/+2
In some cases the link on the system interface of the aquantia PHY comes up after the link on line interface. The link state loop only checks the line side, which may result in first packet sent being lost. Use aquantia_link_is_up instead, which checks both system and line side on gen 2/3 PHYs to avoid losing the 1st packet. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09drivers: net: aquantia: set SMBus addr based on DT propertyAlex Marginean1-0/+15
Aquantia PHYs have a SMBus interface mostly used for debug. The addresses on this interface are normally set up by PHY firmware, but depending on the board they may end up not being unique. Add an optional DT property used to change SMBus address if needed. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09drivers: net: aquantia: set MDI reversal based on DT propertyAlex Marginean1-0/+39
MDI pins up to the RJ45 connector may be reversed on the board and the default PHY configuration applied by firmware may or may not match that. Add an optional DT property to configure MDI reversal for this case. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09drivers: net: aquantia: set up SI protocol based on interface typeAlex Marginean1-0/+107
If PHY is not ready for data by the time _config is called, reconfigure the PHY system interface to use the proper protocol based on phydev->interface, just in case the defaults set by PHY firmware don't match current configuration. Signed-off-by: Florin Laurentiu Chiculita <florinlaurentiu.chiculita@nxp.com> Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09drivers: net: aquantia: add PHY generation informationAlex Marginean1-0/+11
Uses the data field in phy_driver structure to identify the PHY generation. This is useful for custom configuration as non-generic PHY registers are not 100% compatible between generations. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09drivers: net: aquantia: use XFI, USXGMII interface typesAlex Marginean1-14/+33
The PHY supports XFI and USXGMII, the notable difference being that USX AN is enabled for USXGMII. Legacy code uses XGMII for any 10G proto and detects whether USX AN should be enabled or not using a PHY status register. Keep that functionality too, so we don't break existing drivers. Signed-off-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09net: phy: fix switch vendor nameAnatolij Gustschin1-1/+1
Fix vendor name in MV88E61xx option description. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09net: phy: mv88e61xx: register phy_driver struct for 88E6071Anatolij Gustschin1-0/+12
Support probing and init for 88E6071 switch. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071Anatolij Gustschin1-6/+16
On mv88E6071 the 'EDet' field offset, width and sense control bits are different, adjust the driver to init the PHY control register as needed. This fixes not working link detection and tftp transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09net: phy: mv88e61xx: add CPU port parameter init for 88E6071Anatolij Gustschin1-14/+28
On 88E6071 chip the port status register bit field offsets for duplex and link bits differ. Extend the driver to use 88E6071 specific offset values. The width of bit fields for speed status differ, too. Adapt for proper port speed detection on 88E6071. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Chris Packham <judge.packham@gmail.com> Tested-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09net: phy: mv88e61xx: rework to enable detection of 88E6071 devicesAnatolij Gustschin1-25/+125
Extend the driver to init switch register offsets from variables instead of compile time macros and enable detection of 88E6071 and compatible devices. Ethernet transfer (e.g. tftp) does not work yet, so enable the registration of the 'indirect mii' bus for easier PHY register access by 'mii' command. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09net: phy: micrel: make sure the factory test bit is clearedNicolas Ferre1-1/+20
The KSZ8081 PHY has a factory test mode which is set at the de-assertion of the reset line based on the RXER (KSZ8081RNA/RND) or TXC (KSZ8081MNX/RNB) pin. If a pull-down is missing, or if the pin has a pull-up, the factory test mode should be cleared by manually writing a 0 (according to the datasheet). Create another ksz8081_config function to handle this case. Suggested-by: Antoine Tenart <antoine.tenart@bootlin.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09net: phy: aquantia: wait for phy init sequence to finishFlorin Chiculita1-0/+15
Aquantia quad-phys may take longer to initialize. This commit adds a polling mechanism for a global alarm bit that tells if phy init sequence is completed. Signed-off-by: Florin Chiculita <florinlaurentiu.chiculita@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09net: phy: Increase link up delay in genphy_update_link()Stefan Roese1-2/+2
I've noticed that in most cases when genphy_update_link() is called, the ethernet driver (mt7628-eth in this case) fails with the first ethernet packets. Resulting in a timeout of the first tftp command. Increasing the delay in the link check look from 1 to 50 ms and moving it below the BMSR register read fixes this issue, resulting in a stable ethernet traffic, even after initial link autonogotiation. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Weijie Gao <weijie.gao@mediatek.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09net: phy: dp83867: refactor rgmii configurationGrygorii Strashko1-39/+36
Refactor SGMII configuration to group all settings together and reduce number of MDIO transactions. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09net: phy: dp83867: io impedance is not dependent on RGMII delayGrygorii Strashko1-10/+10
Based on commit 27708eb5481b ("net: phy: dp83867: IO impedance is not dependent on RGMII delay") of mainline linux kernel. The driver would only set the IO impedance value when RGMII internal delays were enabled. There is no reason for this. Move the IO impedance block out of the RGMII delay block. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09net: phy: dp83867: rework delay rgmii delay handlingGrygorii Strashko1-12/+64
Based on commit c11669a2757e ("net: phy: dp83867: Rework delay rgmii delay handling") of mainline linux kernel. The current code is assuming the reset default of the delay control register was to have delay disabled. This is what the datasheet shows as the register's initial value. However, that's not actually true: the default is controlled by the PHY's pin strapping. This patch: - insures the other direction's delay is disabled If the interface mode is selected as RX or TX delay only - validates the delay values and fail if they are not in range - checks if the board is strapped to have a delay and is configured to use "rgmii" mode and warning is generated that "rgmii-id" should have been used. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09net: phy: dp83867: Add ability to disable output clockGrygorii Strashko1-17/+36
Based on commit 13c83cf8af0d ("net: phy: dp83867: Add ability to disable output clock") of mainline linux kernel. Generally, the output clock pin is only used for testing and only serves as a source of RF noise after this. It could be used to daisy-chain PHYs, but this is uncommon. Since the PHY can disable the output, make doing so an option. I do this by adding another enumeration to the allowed values of ti,clk-output-sel. The code was not using the value DP83867_CLK_O_SEL_REF_CLK as one might expect: to select the REF_CLK as the output. Rather it meant "keep clock output setting as is", which, depending on PHY strapping, might not be outputting REF_CLK. Change this so DP83867_CLK_O_SEL_REF_CLK means enable REF_CLK output. Omitting the property will leave the setting as is (which was the previous behavior in this case). Out of range values were silently converted into DP83867_CLK_O_SEL_REF_CLK. Change this so they generate an error. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09net: phy: dp83867: move static initialization to .probe()Grygorii Strashko1-12/+17
Move static, one-time initialization to .probe() callback. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09net: phy: ti: rename ti.c to dp83867.cGrygorii Strashko2-1/+1
The driver ti.c is actually driver for TI DP83867x PHYs, so rename it accordingly. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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