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2021-06-23arm64: zynqmp: Remove can aliases from zc1751Michal Simek2-4/+0
Networking subsystem is not using aliases that's why remove them for CAN devices. There is also no any other Xilinx ZynqMP DT file with them. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23arm64: zynqmp: Remove si5328 and si5382 nodesMichal Simek5-40/+5
There are no drivers for these devices that's why remove that nodes completely. This change is done based on Linux kernel. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/20210308115437.2232847-1-quanyang.wang@windriver.com
2021-06-23xilinx: Convert xlnx,eeprom property to nvmem aliasMichal Simek17-18/+19
Convert all boards to use nvmem alias instead of xlnx,eeprom. The change is done based on discussion in the link below. Link: https://lore.kernel.org/r/CAL_JsqLMDqpkyg-Q7mUfw-XH67-v068Q6e9wTq2UOoN=0-_coQ@mail.gmail.com Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23arm64: zynqmp: rtc: Update rtc calibration valueSrinivas Neeli1-1/+1
As per the design specification "The 16-bit Seconds Calibration Value represents the number of Oscillator Ticks that are required to measure the largest time period that is less than or equal to 1 second. For an oscillator that is 32.768 KHz, this value will be 0x7FFF." Signed-off-by: Srinivas Neeli <srinivas.neeli@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23arm64: zynqmp: Sync psgtr location on zcu100/zcu106Michal Simek2-14/+14
psgtr node should be below pinctrl for easier comparion among dts files. That's why move that nodes to different location. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23arm64: zynqmp: Sync dp port location on zc1751 dc4Michal Simek1-9/+9
Historically dpdma and dpsub are placed at the end of files. Move nodes there for easier comparison among dts files. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23arm64: zynqmp: Remove unused dp_aclk clockMichal Simek1-8/+1
dp_aclk is not used anywhere that's why remove it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23arm64: zynqmp: Remove addition newline from zc1751 dc1Michal Simek1-1/+0
Trivial patch. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23arm64: zynqmp: Add maximum-speed property for dwc3 nodesMichal Simek5-0/+5
dwc3 can be used only for higher speeds than super-speed that's why explicitly set it up. This is also aligned with other ZynqMP dts files. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23arm64: zynqmp: Remove additional header from zc1232 DTMichal Simek1-1/+0
Remove unused phy.h from zc1232 DTS. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23zynqmp: Remove u-boot,dm-pre-reloc for uart instancesMichal Simek7-11/+0
Uarts already have u-boot,dm-pre-reloc via zynqmp.dtsi that's why there is no need to have them in platform DT files too. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23zynqmp: Pass bl32 entry to TF-A via xilinx handoff structureMichal Simek1-5/+14
There is need to pass entry about secure OS when bl32_entry is defined. Currently only 64bit support is added but /fit-images node have been extended to also record if this is 32bit or 64bit secure OS. When this is tested the code will be update to support this configuration too. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23zynqmp: Generate u-boot.its also with TEE dynamicallyMichal Simek1-1/+40
The first change is to trying to find out TF-A load address based on reading elf file. Expectation is that bl31.bin is in the same folder as bl31.elf. It brings new flexibility to place TF-A to any address (DDR included). And also enable TEE generation also with TEE configuration. Expecation is the same as above that tee.bin and tee.elf are in the same folder. User has to just define link to BL31/BL32 binary files and the rest should be handled by the script. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23arm64: zynqmp: Update Copyright years to 2021Michal Simek16-16/+16
Trivial change for all files I have touched recently. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23arm64: zynqmp: Add label for zynqmp_ipiMichal Simek1-1/+1
Add label which is used by bootloader for adding bootloader specific flag. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/3dc8416abdd3498e61edcd83830a12af295c5c6d.1611224800.git.michal.simek@xilinx.com
2021-06-23arm64: zynqmp: Move DP nodes to the end of file (zcu106)Michal Simek1-11/+11
Just sync it with others for easier comparison. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23arm64: zynqmp: Add reset description for sataMichal Simek1-0/+1
Sata needs to get reset before configuration that's why add property for it there. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23arm64: zynqmp: Add missing SMID for pcie to zynqmp.dtsiStefano Stabellini1-0/+2
The SMMU is disabled in device tree so this change has no impact. The benefit is that this way it is in sync with xen.dtsi. Xen enables the SMMU and makes use of it. Signed-off-by: Stefano Stabellini <stefano.stabellini@xilinx.com>
2021-06-23arm64: zynqmp: Disable CCI by defaultMichal Simek1-0/+1
There is no reason to have CCI no enabled by default. Enable it when your system configuration requires it. In Xilinx configuration flow this is work for Device Tree Generator which reads information from HW Design configuration. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23arm64: zynqmp: Update psgtr clocks index for boardsMichal Simek5-29/+29
Update the psgtr clock indexing for couple of zynqmp boards. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23ARM: zynq: Rename bus to be align with simple-bus yamlMichal Simek1-1/+1
Rename amba to AXI. Based on Xilinx Zynq TRM (Chapter 5) chip is "AXI point-to-point channels for communicating addresses, data, and response transactions between master and slave clients. This ARM AMBA 3.0..." Issues are reported as: .. amba: $nodename:0: 'amba' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' >From schema: ../github.com/devicetree-org/dt-schema/dtschema/schemas/simple-bus.yaml Similar change has been done for Xilinx ZynqMP SoC. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/8a4bc80debfbb79c296e76fc1e4c173e62657286.1606397101.git.michal.simek@xilinx.com
2021-06-23arm64: zynqmp: Enable gpio driver for zcu1275/zcu1285Michal Simek3-0/+12
Enable gpio driver on these boards. GPIOs can be used on any board. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23arm64: zynqmp: Fix application loading on R5 core1Ashok Reddy Soma1-31/+39
From U-Boot, loading application on RPU core 0 is fine but loading on core 1 is not handled properly. Lock-step mode needs both the R5 cores to be initialized and it is working fine. Whereas in SPLIT mode individual R5 cores needs to be initialized as they need to execute differenet applications. Handle both these lock-step and split modes by propagating mode and RPU core number(4 for RPU0 and 5 for RPU1) for various functions and by adding conditions in those functions. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23ARM: zynq: Fix OCM mapping to be aligned with binding on zc702Michal Simek1-0/+6
The Linux commit f69629919942 ("dt-bindings: sram: Convert SRAM bindings to json-schema") converted binding to yaml and some missing required properties started to be reported. Align binding based on it. The patch is fixing these warnings: .../zynq-zc702.dt.yaml: sram@fffc0000: '#address-cells' is a required property .../zynq-zc702.dt.yaml: sram@fffc0000: '#size-cells' is a required property .../zynq-zc702.dt.yaml: sram@fffc0000: 'ranges' is a required property >From schema: .../Documentation/devicetree/bindings/sram/sram.yaml Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/87c02786ccd8d7827827a9d95a8737bb300caeb0.1606397101.git.michal.simek@xilinx.com
2021-06-23ARM: zynq: Convert at25 binding to new description on zc770-xm013Michal Simek1-4/+3
The Linux commit f8f79fa6bb25 ("dt-bindings: at25: convert the binding document to yaml") converted binding to yaml and 3 deprecated properties pop up. The patch is fixing these warnings: .../zynq-zc770-xm013.dt.yaml: eeprom@2: 'pagesize' is a required property .../zynq-zc770-xm013.dt.yaml: eeprom@2: 'size' is a required property .../zynq-zc770-xm013.dt.yaml: eeprom@2: 'address-width' is a required property >From schema: .../Documentation/devicetree/bindings/eeprom/at25.yaml by converting them to new binding. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/be2c1125d98386033e182012eb08986924707a76.1606397101.git.michal.simek@xilinx.com
2021-06-23zynqmp: spl: support DRAM ECC initializationJorge Ramirez-Ortiz6-0/+218
Use the ZDMA channel 0 to initialize the DRAM banks. This avoid spurious ECC errors that can occur when accessing unitialized memory. The feature is enabled by setting the option CONFIG_SPL_ZYNQMP_DRAM_ECC_INIT and providing the following data: SPL_ZYNQMP_DRAM_BANK1_BASE: start of memory to initialize SPL_ZYNQMP_DRAM_BANK1_LEN : len of memory to initialize (hex) SPL_ZYNQMP_DRAM_BANK2_BASE: start of memory to initialize SPL_ZYNQMP_DRAM_BANK2_LEN : len of memory to initialize (hex) Setting SPL_ZYNQMP_DRAM_BANK_LEN to 0 takes no action. Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-21ARM: dts: k3-j7200-common-proc-board-u-boot.dtsi: Fix dtc warningsVignesh Raghavendra1-0/+2
Fix following dtc warning by explicitly setting up #size-cells and #address-cells when overriding node in -u-boot.dtsi arch/arm/dts/k3-j7200-common-proc-board.dtb: Warning (reg_format): /bus@100000/bus@28380000/mcu-navss/ringacc@2b800000:reg: property has invalid length (80 bytes) (#address-cells == 2, #size-cells == 1) Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-06-21o4-imx-nano: Fix dtc warningsFabio Estevam1-12/+6
Remove the LED unit addresses and reg properties to fix the following dtc build warnings: arch/arm/dts/o4-imx-nano.dtb: Warning (reg_format): /leds/led@0:reg: property has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1) ... arch/arm/dts/o4-imx-nano.dtb: Warning (avoid_default_addr_size): /leds/led@0: Relying on default #address-cells value Reported-by: Tom Rini <trini@konsulko.com> Signed-off-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Oleh Kravchenko <oleg@kaa.org.ua>
2021-06-19Merge tag 'u-boot-rockchip-20210618' of ↵Tom Rini18-0/+5481
https://source.denx.de/u-boot/custodians/u-boot-rockchip into next - New SoC platform support: rk3568; - rockchip pcie Code compile issue fix; - Board fix for rk3399 Khadas Edge; - Add Rockchip NFC driver;
2021-06-18net: use the same alias stem for ethernet as linuxMichael Walle2-11/+11
Linux uses the prefix "ethernet" whereas u-boot uses "eth". This is from the linux tree: $ grep "eth[0-9].*=.*&" arch/**/*dts{,i}|wc -l 0 $ grep "ethernet[0-9].*=.*&" arch/**/*dts{,i}|wc -l 633 In u-boot device trees both prefixes are used. Until recently the only user of the ethernet alias was the sandbox test device tree. This changed with commit fc054d563bfb ("net: Introduce DSA class for Ethernet switches"). There, the MAC addresses are inherited based on the devices sequence IDs which is in turn given by the device tree. Before there are more users in u-boot and both worlds will differ even more, rename the alias prefix to "ethernet" to match the linux ones. Also adapt the test cases and rename any old aliases in the u-boot device trees. Cc: David Wu <david.wu@rock-chips.com> Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-06-18stm32mp: stm32prog: handle dfu errorPatrick Delaunay1-0/+14
Handle DFU stack error in STM32CubeProgrammer protocol. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-06-18stm32mp: stm32prog: change one message level to debugPatrick Delaunay1-1/+1
Move the message "Invalid or missing layout file." to debug level as it is a normal behavior and not an error and add the missing '\n'. This patch avoids the strange trace : Boot over usb0! Invalid or missing layout file.DFU alt info setting: done Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-06-18stm32mp: stm32prog: use get_cpu_dev for GetID commandPatrick Delaunay1-4/+6
Use get_cpu_dev() in uart getID command and remove the defines DEVICE_ID_BYTE1 and 2 defines. This patch prepare the support for new SOC family. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-06-18stm32mp: stm32prog: correctly handle DM_PMICPatrick Delaunay1-1/+4
Correctly handle number of alternate when DM_PMIC is not activated. This patch remove the last UNKNOWN partition in this case. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-06-18stm32mp: stm32prog: handle the next phase after USB re-enumerationPatrick Delaunay1-5/+2
Handle the second USB enumeration only when the flashlayout is received and when phase is PHASE_FLASHLAYOUT. This patch removes the call of stm32prog_next_phase as it is already done in stm32prog_dfu_init(). Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-06-18stm32mp: stm32prog: solve compilation with CONFIG_FIT_SIGNATUREPatrick Delaunay1-0/+2
When CONFIG_FIT_SIGNATURE is activated, CONFIG_LEGACY_IMAGE_FORMAT is deactivated and the define IMAGE_FORMAT_LEGACY don't exist with include/image.h: #if defined(CONFIG_LEGACY_IMAGE_FORMAT) #define IMAGE_FORMAT_LEGACY 0x01 /* legacy image_header based format */ #endif This patch adds the needed check on compilation flag CONFIG_LEGACY_IMAGE_FORMAT to avoid the compilation error for command stm32prog: cmd_stm32prog.c:81:8: error: ‘IMAGE_FORMAT_LEGACY’ undeclared (first use in this function); did you mean ‘IMAGE_FORMAT_FIT’? 81 | if (IMAGE_FORMAT_LEGACY == | ^~~~~~~~~~~~~~~~~~~ | IMAGE_FORMAT_FIT Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-06-18stm32mp: stm32prog: add support of initrd in flashlayoutPatrick Delaunay3-10/+24
Add the support in command stm32prog of kernel load and start with initrd file, identify by the partition Type "Binary" in the flashlayout.tsv, for example: - 0x01 fsbl Binary none 0x0 tfa.stm32 - 0x03 fip Binary none 0x0 fip.bin P 0x10 kernel System ram0 0xC2000000 uImage.bin P 0x11 dtb FileSystem ram0 0xC4000000 board.dtb P 0x12 initrd Binary ram0 0xC4400000 <initrd> The <initrd> file can be a legacy image "uInitrd", generated with mkimage, or a RAW initrd image "initrd.gz". After a DFU detach the bootm command with be executed with the associated address, for example: $> bootm 0xC2000000 0xC4400000:<size> 0xC4000000 When the "Binary" partition type is absent, the 'bootm' command starts the kernel without ramdisk, for example: $> bootm 0xC2000000 - 0xC4000000 With this paths, it is no more mandatory to generate FIT including the kernel, DT and initrd: - 0x01 fsbl Binary none 0x0 tfa.stm32 - 0x03 fip Binary none 0x0 fip.bin P 0x10 fit System ram0 0xC2000000 fit.bin Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-06-18stm32mp: stm32prog: add timeout in stm32prog_serial_get_bufferPatrick Delaunay1-2/+10
Handle timeout in stm32prog_serial_get_buffer to sent NACK to STM32CubeProgrammer when the buffer is not fully received. This patch avoids to reach the STM32CubeProgrammer timeout and the associated unrecoverable error. Timeout error occurred while waiting for acknowledgment. Error: Write Operation fails at packet number 4165 at address 0x1044FF Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-06-18stm32mp: stm32prog: remove all the header check for UART downloadPatrick Delaunay3-148/+22
This patch removes the header check for UART download; the check of checksum is not mandatory with even parity and chuck checksum for each 256 received bytes and it is only done for STM32 image (FSBL = TF-A BL2), not for FIT image. This patch solve issue of duplicated 0x100 byte written with FIP header. Fixes: 4fb7b3e10891 ("stm32mp: stm32prog: add FIP header support") Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-06-18board: rockchip: Add rk3568 evb supportJoseph Chen1-0/+1
Add support for rk3568 evaluation board. Signed-off-by: Joseph Chen <chenjh@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-06-18rockchip: Add rk3568 architecture coreJoseph Chen10-0/+600
RK3568 is a high-performance and low power quad-core application processor designed for personal mobile internet device and AIoT equipments. Signed-off-by: Joseph Chen <chenjh@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-06-18arm: dts: rockchip: Add dts for rk3568 evbJoseph Chen6-0/+4032
Add dts for rk3568 evb, sync from the linux kernel upstream list [0]. [0] https://patchwork.kernel.org/project/linux-rockchip/list/?series=474969 Signed-off-by: Joseph Chen <chenjh@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-06-18arm: dts: Sync rockchip-pinconf.dtsi from kernelJoseph Chen1-0/+344
Sync from linux kernel: https://patchwork.kernel.org/project/linux-rockchip/list/?series=474969 Signed-off-by: Joseph Chen <chenjh@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-06-18rockchip: rk3568: add clock driverElaine Zhang1-0/+504
Add rk3568 clock driver and cru structure definition. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-06-18arm: dts: stm32mp157c-odyssey-som: enable SDMMC2 in SPLGrzegorz Szymaszek1-0/+21
Enable the SDMMC2 device tree node, as well as the pins it uses, in U-Boot SPL. Signed-off-by: Grzegorz Szymaszek <gszymaszek@short.pl> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-06-18arm: dts: stm32mp157c-odyssey-som: enable the SDMMC2 eMMC HS DDR modeGrzegorz Szymaszek1-0/+1
Enable the SDMMC2 eMMC high-speed DDR mode as it is done in the corresponding Linux kernel device tree. Signed-off-by: Grzegorz Szymaszek <gszymaszek@short.pl> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-06-18arm: dts: stm32mp157c-odyssey-som: set the SDMMC2 VQMMC supplyGrzegorz Szymaszek1-0/+1
Set the SDMMC2 VQMMC supply to vdd (buck3). Note that in the corresponding Linux kernel device tree, the supply is set to v3v3 (buck4), which is wrong. Signed-off-by: Grzegorz Szymaszek <gszymaszek@short.pl> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-06-18arm: dts: stm32mp157c-odyssey-som: enable all SDMMC2 data lanesGrzegorz Szymaszek1-4/+4
Add the “sdmmc2_d47_pins_d” pins to the SDMMC2 pinctrls. Increase the bus width from four to eight. Signed-off-by: Grzegorz Szymaszek <gszymaszek@short.pl> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-06-18arm: dts: stm32mp157c-odyssey-som: fix the basic SDMMC2 propertiesGrzegorz Szymaszek1-2/+3
The SDMMC2 interface hosts an eMMC. Replace the interface properties that would only apply to SD cards—“broken-cd” and “disable-wp”—with relevant ones: “non-removable”, “no-sd” and “no-sdio”. Signed-off-by: Grzegorz Szymaszek <gszymaszek@short.pl> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-06-17Merge tag 'u-boot-atmel-2021.10-a' of ↵Tom Rini1-2/+2
https://source.denx.de/u-boot/custodians/u-boot-atmel into next First set of u-boot-atmel features for the 2021.10 cycle: This feature set converts the boards pm9261 and pm9263 Ethernet support to DM; enables hash command for all SAM boards; fixes the NAND pmecc bit-flips correction; adds Falcon boot for sama5d3_xplained board; and other minor adjustments.
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