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2023-01-05dts: add i2c5 and attach pmic configurationminda.chen2-0/+20
i2c5 and pmic is used by opensbi power management ops. Signed-off-by: minda.chen <minda.chen@starfivetech.com>
2023-01-03dts: pmu : add riscv pmu dts configminda.chen1-0/+46
add 7110 performance monitor for perf use Signed-off-by: minda.chen <minda.chen@starfivetech.com>
2022-12-14board:starfive:jh7110: default cpufreq is 1000Mhz.Samin Guo1-1/+1
The frequency of pll0 is set to 1000Mhz in the bootrom Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2022-11-23dts:starfive:Add pinctrl configJianlong Huang2-7/+59
Add pinctrl config about usb/sdio0 Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
2022-11-01board:starfive:evb: add get_chip_typeSamin Guo1-0/+2
Read the chip model from the rgpio3 and setenv "chip_vision" 1: jh7110B 0: JH7110A defalut: JH7110A Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2022-11-01board:starfive:evb: add jh7110_gmac_sel_tx_to_rgmiiSamin Guo1-0/+8
JH7110B needs switch gmac0/1 tx to rgmii phy. Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2022-11-01dts:starfive:jh7110: set gmac phy tx_inverted for JH7110A/B.Samin Guo1-1/+11
JH7110B requires tx_inverted_10/100/1000 configuration, and different parameters may be required in 10M/100M/1000M mode. This parameter supports JH7110B+YT8531PHY by default. Other boards can modify the parameters of the tx_inverted_10/100/1000 to obtain support. If you do not configure tx_inverted_10/100/1000 in dts, the default is 0. Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2022-10-18riscv: dts: jh7110: Add reset property to DDR control nodeYan Hong Wang1-1/+5
Add reset property configuration to DDR control device tree node. Signed-off-by: Yan Hong Wang <yanhongwang@linux.starfivetech.com>
2022-10-18arch: riscv: jh7110: add pll clk configuration for jh7110Yan Hong Wang4-18/+416
Add common interface to set and get pll clk information for jh7110 soc. Signed-off-by: Yan Hong Wang <yanhong.wang@starfivetech.com>
2022-10-18riscv:dts:starfive-jh7110: modify Model and riscv,isa infoyanhong.wang2-6/+6
Change Model to "StarFive JH7110 EVB", and change riscv,isa to "rv64imafdcbsux" Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18board:starfive:evb: update uart3-uart5 resetsyanhong.wang1-6/+12
Add SPL_DM_RESET to defconfig, and update uart3-uart5 reset for StarFive JH7110 SoC. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18SPL:starfive-jh7110: Modify the default division factor of sdcard clkyanhong.wang1-0/+4
Modify the default division factor of sdcard clk to 4. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18board:starfive:evb: add usb init configyanhong.wang1-0/+18
Add usb init config for starfive EVB board. Default set to USB2.0 Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18clk:starfive-jh7110: Update pll0/pll1/pll2 clkyanhong.wang1-18/+0
Remove pll0/pll1/pll2 clk define from jh7110_clk.dts to clk-jh7110.c Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18spl: satrfive: bus_root switch to pll2.samin1-5/+0
High-speed emmc/sdio support Signed-off-by: samin <samin.guo@starfivetech.com>
2022-10-18board:starfive:evb: modify the GPIO configuration for sd moduleyanhong.wang1-0/+5
Modify the GPIO configuration for sd&emmc module, switch the clk of sd&emmc to high frequency Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18riscv:dts:starfive-jh7110: Modify sd node configurationyanhong.wang4-38/+7
Modify SD&EMMC node configuration on Starfive EVB board. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18SPL:riscv:starfive-jh7110: Adjust CPU working frequencyyanhong.wang2-1/+18
Adjust CPU working frequency from 1G to 1.25G for starfive EVB board. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18riscv:dts:starfive-jh7110: add ethernet-phy delay_chain configyanhong.wang2-4/+17
Add ethernet-phy delay_chain configuration for gmac1 on starfive EVB board. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18riscv:starfive-jh7110: clear L2 LIM memoryyanhong.wang1-0/+14
Clear L2 LIM memory on StarFive JH7110, avoid some unexpect exception.
2022-10-18riscv:dts:starfive-jh7110: add ddr device nodeyanhong.wang1-0/+7
Add ddr device node for JH7110. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18board:starfive: add clk inityanhong.wang1-5/+27
Add clk init for ddr on JH7110 board Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18clk:starfive-jh7110: Update pll0/pll1/pll2 clkyanhong.wang2-3/+22
Add JH7110_GMAC0_GTXC clk register and remove pll0/pll1/pll2 clk define from clk-jh7110.c to jh7110_clk.dts Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18GPIO:Starfive-jh7110: Add macro definitionyanhong.wang1-0/+21
Add macro definition of GPIO Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18board:starfive: add starfive evb board supportyanhong.wang5-0/+153
Add board support for StarFive EVB. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18riscv:dts: update clk&reset propertiesyanhong.wang2-157/+443
Synchronize the kernel dts file Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18riscv:dts: update clk&reset propertiesyanhong.wang2-53/+182
Synchronize the kernel dts file Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18board:starfive: add rtc timer inityanhong.wang1-0/+16
The rtc timer is used early in kernel, but the clk&reset driver is not ready,so some clk&reset init is placed here. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18board:starfive: add starfive visionfive board supportyanhong.wang2-0/+49
Add board support for StarFive VisionFive. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18riscv:dts: add jh7110 supportyanhong.wang6-0/+1341
Add dts support for jh7110. The starfive visionfive support is based on jh7110 soc. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18riscv:soc:jh7110: Add support jh7110 soc.yanhong.wang7-0/+180
Add StarFive JH7110 soc to support RISC-V arch Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18GPIO:Starfive-jh7110: Add GPIO driver for JH7110yanhong.wang1-0/+53
Support for GPIO controller on starfive JH7110 SoCs. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2021-09-29Merge tag 'rpi-next-2021.10.2' of ↵Tom Rini1-0/+6
https://source.denx.de/u-boot/custodians/u-boot-raspberrypi - fix usb stopt; usb start; bug - update Nicolas email address
2021-09-29arm: rpi: perform XHCI firmware upload only onceMarek Szyprowski1-0/+6
XHCI firmware upload must be performed only once after initializing the PCI bridge. This fixes USB stack initialization after calling "usb stop; usb start" on Raspberry Pi 4B. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Nicolas Saenz Julienne <nsaenz@kernel.org> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2021-09-29arm: dts: armada8040: Fix CP0 eMMC/SDIO supportRobert Marko1-2/+2
During the migration to a single DTSI for the CP110-s specific pinctrl compatibles were moved to the SoC DTSI as CP0 and CP1 have some specifics. Namely, CP0 eMMC/SDIO support depends on the mvebu-pinctrl driver setting the BIT(0) in eMMC PHY IO Control 0 Register to 0 in order for the connect the eMMC/SDIO PHY to the controller and not use it as a MPP pin multiplexor. So, the mvebu-pinctrl driver check specifically for the "marvell,armada-8k-cpm-pinctrl" compatible to clear the that bit. Issue is that compatibles in the 8040 DTSI were set to "marvell,8k-cpm-pinctrl" for CP0 and "marvell,8k-cps-pinctrl" for the CP1. This is obviously incorrect as the pinctrl driver does not know about these. So fix the regression by applying correct compatibles to the DTSI. Regression found and tested on the Puzzle M801 board. Fixes: a0ba97e5 ("arm: armada: dts: Use a single dtsi for cp110 die description") Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Stefan Roese <sr@denx.de>
2021-09-28imx: imx7d-sdb: fix ethernet, sync .dts with linuxRasmus Villemoes1-3/+3
Commit 0d52bab46 (mx7dsabre: Enable DM_ETH) changed these flags from 0 (aka GPIO_ACTIVE_HIGH) to GPIO_ACTIVE_LOW. It claimed to "Also sync device tree with v5.5-rc1", but in the linux tree, these gpios have always been GPIO_ACTIVE_HIGH ever since this node was introduced around v4.13 (linux commit 184f39b5). I'm guessing that the reason for the GPIO_ACTIVE_LOW was to work around the behaviour of the soft-spi driver back then, which effectively defaulted to spi-mode 3 and not 0. That was arguably a bug in the soft-spi driver, which then got fixed in 0e146993bb3 (spi: add support for all spi modes with soft spi), but that commit then broke ethernet on this board. Fix it by setting the gpios as active high, which as a bonus actually brings us in sync with the .dts in the linux source tree. Without this, one gets Net: Could not get PHY for FEC0: addr 0 No ethernet found. With this, ethernet (at least ping and tftp) works as expected from the U-Boot shell. Cc: Fabio Estevam <festevam@gmail.com> Cc: Joris Offouga <offougajoris@gmail.com> Cc: "Christian Bräuner Sørensen" <yocto@bsorensen.net> Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2021-09-22arm: socfpga: vining: Fix UDC controller phandle in DTMarek Vasut1-1/+1
The USB peripheral controller is the DWC2 controller 1, not 0. Update the phandle to fix UDC support on this board. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
2021-09-22arm: socfpga: vining: Un-disable WDT in DTMarek Vasut1-4/+0
The WDT on this system should be enabled, make it so. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
2021-09-22x86: tangier: acpi: Add GPIO card detection to SDHCI #2Andy Shevchenko1-0/+32
On Intel Tangier the SDHCI #2 provides SD card connection. Add GPIO card detection for it. Fixes: 39665beed6f7 ("x86: tangier: Enable ACPI support for Intel Tangier") BugLink: https://github.com/edison-fw/meta-intel-edison/issues/135 Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Bin Meng <bmeng.cn@gmail.com>
2021-09-22x86: edison: Mark eMMC non-removableAndy Shevchenko1-0/+1
eMMC is non-removable on Intel Edison board. Fix the DTS accordingly. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-09-21arm: dts: stm32mp1: use ssbl partition name for U-BootPatrick Delaunay2-2/+6
Continue to use the "ssbl" name for GPT partition of secondary boot stage = U-Boot for basic boot with SPL to avoid to disturb existing user. The "fip" partition name is only used for TFA_BOOT with FIP, it is a TF-A BL2 requirement; it the default configuration for STMicroelectronics boards. Fixes: b73e8bf453f8 ("arm: stm32mp: add defconfig for trusted boot with FIP") Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-09-17arm: mach-k3: common: Make sure firmware sections are loaded prior to armv8 ↵Nishanth Menon1-12/+18
startup With Device Manager firmware in an elf file form, we cannot load the FIT image to the exact same address as any of the executable sections of the elf file itself is located. However, the device tree descriptions for the ARMV8 bootloader/OS includes DDR regions only the final sections in DDR where the Device Manager firmware is actually executing out of. As the R5 uC is usually operating at a slower rate than an ARMv8 MPU, by starting the Armv8 ahead of parsing the elf and copying the correct sections to the required memories creates a race condition where the ARMv8 could overwrite the elf image loaded from the FIT image prior to the R5 completing parsing and putting the correct sections of elf in the required memory locations. OR create rather obscure debug conditions where data in the section is being modified by ARMV8 OS while the elf copy is in progress. To prevent all these conditions, lets make sure that the elf parse and copy operations are completed ahead of ARMv8 being released to execute. We will pay a penalty of elf copy time, but that is a valid tradeoff in comparison to debug of alternate scenarios. Signed-off-by: Nishanth Menon <nm@ti.com>
2021-09-17arm: mach-k3: am6_init: Prioritize MSMC traffic over DDR in NAVSS NorthbridgeRoger Quadros2-0/+21
NB0 is bridge to SRAM and NB1 is bridge to DDR. To ensure that SRAM transfers are not stalled due to delays during DDR refreshes, SRAM traffic should be higher priority (threadmap=2) than DDR traffic (threadmap=0). This fixup is critical to provide deterministic access latency to MSMC from ICSSG, it applies to all AM65 silicon revisions and is due to incorrect reset values (has no erratum id) and statically setting things up should be done independent of usecases and board. This specific style of Northbridge configuration is specific only to AM65x devices, follow-on K3 devices have different data prioritization schemes (ASEL and the like) and hence the fixup applies purely to AM65x. Without this fix, ICSSG TX lock-ups due to delays in MSMC transfers in case of SR1 devices, on SR2 devices, lockups were not observed so far but high retry rates of ICSSG Ethernet (icssg-eth) and, thus, lower throughput. Signed-off-by: Roger Quadros <rogerq@ti.com> Acked-by: Andrew F. Davis <afd@ti.com> Acked-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Acked-by: Benoit Parrot <bparrot@ti.com> [Jan: rebased, dropped used define, extended commit log] Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> [Nishanth: Provide relevant context in the commit message] Signed-off-by: Nishanth Menon<nm@ti.com>
2021-09-17clk: ti: k3: Update driver to account for divider flagsSuman Anna2-97/+99
The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-09-17arm: mach-k3: Add note to auto-generated filesDave Gerlach4-4/+20
Add a note to the automatically generated clk-data and dev-data files for j721e and j7200 to indicate that they are in fact auto-generated and should not be hand edited. Also adjust TI URL to use https instead of http and also add an empty line before first header inclusion. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-09-17arm: mach-k3: j7200: Fix clk-data parenting for postdiv PLL clocksSuman Anna1-4/+4
The TI K3 Fractional PLLs use two programmable POSTDIV1 and POSTDIV2 divisors to generate the final FOUTPOSTDIV clock. These are in sequence with POSTDIV2 following the POSTDIV1 clock. The current J7200 clock data has the POSTDIV2 clock as the parent for the POSTDIV1 clock, which is opposite of the actual implementation. Fix the data by simply adjusting the register bit-shifts. The Main PLL1 POSTDIV clocks were also defined incorrectly using Main PLL0 register values, fix these as well. Fixes: 277729eaf373 ("arm: mach-k3: Add platform data for j721e and j7200") Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-09-17arm: mach-k3: j721e: Fix clk-data parenting for postdiv PLL clocksSuman Anna1-4/+4
The TI K3 Fractional PLLs use two programmable POSTDIV1 and POSTDIV2 divisors to generate the final FOUTPOSTDIV clock. These are in sequence with POSTDIV2 following the POSTDIV1 clock. The current J721E clock data has the POSTDIV2 clock as the parent for the POSTDIV1 clock, which is opposite of the actual implementation. Fix the data by simply adjusting the register bit-shifts. The Main PLL1 POSTDIV clocks were also defined incorrectly using Main PLL0 register values, fix these as well. Fixes: 277729eaf373 ("arm: mach-k3: Add platform data for j721e and j7200") Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-09-17arm: mach-k3: common: Add a release_resources_for_core_shutdown() stubSuman Anna1-0/+5
Add a weak release_resources_for_core_shutdown() stub implementation that can be overridden by actual implementation if a SoC supports that function. Signed-off-by: Suman Anna <s-anna@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com>
2021-09-15ARM: bcm283x: change the virtual address of the XHCI PCI device baseMarek Szyprowski1-2/+2
Move the XHCI PCI device base up in the virtual address space. This fixes initialization failure observed with newer Raspberry Pi firmware, later than 63b1922311 ("firmware: arm_loader: Update armstubs with those from PR 117). It looks that chosing 0xff800000 as the XHCI PCI device base conflicts with the updated ARM/VideoCore firmware. This also requires to reduce the size of the mapped PCI device region from 8MiB to 4MiB to fit into 32bit address space. This is still enough for the XHCI PCI device. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Nicolas Saenz Julienne <nsaenz@kernel.org> Tested-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2021-09-15arm: dts: bcm283x: Add minimal smbios informationMatthias Brugger1-0/+19
At present SMBIOS tables are empty, which breaks some use-cases that rely on that. Add some minimal information to fulfill this. Signed-off-by: Matthias Brugger <mbrugger@suse.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-12 06:02:36 +0300