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2021-04-06Merge tag 'rockchip-for-v2021.07' of ↵Tom Rini15-300/+963
https://source.denx.de/u-boot/custodians/u-boot-rockchip - Fix rk3368 lion board support; - Fix px30 odroid-go2 board support; - Add rk3399 NanoPi R4s and NanoPi M4B board support;
2021-04-05Merge branch 'next'Tom Rini179-1191/+3468
2021-03-31Merge tag 'xilinx-for-v2021.07' of ↵Tom Rini22-258/+511
https://source.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2021.07 net: - Fix gem PCS support spi: - Small trivial fixes zynq: - Enable time/timer commands - Update bitmain platform - Several DT changes zynqmp: - Update clock driver - mini config alignments - Add/update psu_init for zcu208/zcu216/zc1275 - Several DT changes - Enable efi debug command (also for Versal)
2021-03-31sunxi: dts: H616: Drop reserved-memory nodeAndre Przywara1-12/+0
Trusted Firmware now adds the /reserved-memory subnode to the DT at runtime[1], putting in the right values. Drop our hard-coded version, as this might clash with the actual values (which have also changed), and rely on TF-A to add the node. [1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/7770 Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-03-31sunxi: H616: Change TF-A load address to beginning of DRAMAndre Przywara1-1/+1
Loading Trusted-Firmware's BL31 at 16KB into DRAM was originally a hack to allow sharing more code with the other SoCs (which use this offset in SRAM). However there is no longer a reason for that, as the problematic macros have been properly separated there. The latest (and hopefully final) TF-A code drop now changes the load address to the beginning of DRAM, which is also more easily protected by the Trustzone memory controller (code to be done). Adjust the load address of BL31 now, to avoid any issues with incompatible versions later on (the TF-A patches are about to be merged). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Samuel Holland <samuel@sholland.org>
2021-03-30Merge tag 'u-boot-atmel-2021.07-a' of ↵Tom Rini2-8/+9
https://source.denx.de/u-boot/custodians/u-boot-atmel into next First set of u-boot-atmel features for 2021.07 cycle: This small feature set includes the implementation of the slew rate for the PIO4 pin controller device, and a fix for arm926ejs-based microprocessors that avoids a crash.
2021-03-30ARM: bitmain: Enable nand and smcc driversMichal Simek1-0/+8
Enable nand and smcc via DT. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-03-30xilinx: Sync DTs with Linux kernelMichal Simek18-255/+482
There are several changes which happen in mainline kernel which should get also to U-Boot. Here is the list of patches from the kernel: - ARM: zynq: Fix leds subnode name for zc702/zybo-z7 - arm64: dts: zynqmp: Fix leds subnode name for zcu100/ultra96 v1 - arm64: dts: zynqmp: Fix u48 si5382 chip on zcu111 - arm64: dts: zynqmp: Wire up the DisplayPort subsystem - arm64: dts: zynqmp: Add DisplayPort subsystem - arm64: dts: zynqmp: Add DPDMA node - arm64: dts: zynqmp: Enable phy driver for Sata on zcu102/zcu104/zcu106 - arm64: dts: zynqmp: Enable si5341 driver for zcu102/106/111 - arm64: dts: zynqmp: Add DT description for si5328 for zcu102/zcu106 - arm64: dts: zynqmp-zcu100-revC: correct interrupt flags - arm64: dts: xilinx: align GPIO hog names with dtschema - arm64: zynqmp: Add Xilinx AES node - dt: bindings: dma: xilinx: dpdma: DT bindings for Xilinx DPDMA but also some other changes have been done. - Using only one compatible string for adxl345 on zturn - Remove Xilinx internal DP bindings - Remove USB3.0 serdes configurations - Remove SATA serdes configuration for zc1232 - Resort nvmem_firmware - Update nand compatible string - Aling power-domains property for sd0/1 Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-03-30arm64: zynqmp: Rename clocks as per the Arasan NAND driverAmit Kumar Mahapatra1-1/+1
In zynqmp.dtsi file renamed "clk_sys" clock to "controller" and "clk_flash" clock to "bus" as per upstreamed Arasan NAND driver. This fixes NAND driver probe failure. Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-03-30arm64: zynqmp: Update device tree properties for nand flashAmit Kumar Mahapatra1-0/+8
Update the following device tree properties for nand flash - Set software ecc mode. - Set bch as ecc algo. - Set read block to 0. Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-03-30arm64: zynqmp: Add idt 8a34001 chip to zcu208/zcu216Michal Simek2-2/+8
There is Linux driver for these chips that's why add it to device tree. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-03-30arm64: zynqmp: Add emmc specific parametersAshok Reddy Soma2-0/+4
EMMC will have bus-width 8 and it is non-removable in general. These are missing from dt node. Add bus-width and non-removable parameters to emmc node. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-03-30board: dts: rockchip: Add NanoPi M4BAlexandre Vicenzi3-0/+60
Add initial support for NanoPi M4B, a minor revision of the original NanoPi M4. Commit details of rk3399-nanopi-m4b.dts sync from Linux 5.12-rc4: "arm64: dts: rockchip: Add NanoPi M4B board" (sha1: c7b03115003f7f337ab165542cee37148cf30a8a) Signed-off-by: Alexandre Vicenzi <alexandre.vicenzi@suse.com> Reviewed-by: Kever Yang <kever.yang@rock-cihps.com>
2021-03-30arm64: rk3399: Add support NanoPi R4sXiaobo Tian3-0/+155
NanoPi R4s is SBC base on Rockchip RK3399 hexa-core processor with dual-Core Cortex-A72 and Mali-T864 GPU with 4GiB(LPDDR4) of RAM, SD card support, including 2 gigabit ethernet(RTL8211E 1Gbps - RTL8111H 1Gbps) and 2 USB 3.0 port. port.It also has two GPIO headers which allows further peripherals to be used. The devicetree file is taken of the rk3399 nanopi4 Linux kernel [1]. [1] https://github.com/torvalds/linux/commit/e7a095908227fb3ccc86d001d9e13c9ae2bef8e6 Signed-off-by: xiaobo <peterwillcn@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-03-30rockchip: rk3399-puma: Restore correct VDD_LOG supply.Christoph Muellner1-0/+12
A commit from last year re-imported the DTS files form the upstream kernel. By doing so the VDD_LOG regulator in the board's DTS was dropped. Let's restore this, but move it into the u-boot overlay to prevent this issue in the future. Fixes: 167efc2c7a46 ("arm64: dts: rk3399: Sync v5.7-rc1 from Linux") Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com> Reviewed-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-03-30rockchip: rk3368: sync down rk3368-lion board devicetree from LinuxHeiko Stuebner4-68/+349
This brings the actual rk3368-lion devicetree files from Linux 5.10 instead of using something separate. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-03-30rockchip: rk3368: sync main rk3368 dtsi from LinuxHeiko Stuebner6-231/+383
This is the state as of v5.10 + the recently added timer0 phandle targetted at the 5.12 merge window. With this the non-mainline nodes like the dmc move to a separate rk3368-u-boot.dtsi that is included from the board-specific -u-boot.dtsi files, similar to how rk3399 does this. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-03-30rockchip: rk3368: move STACK_R_ADDR address and into KconfigHeiko Stuebner1-0/+3
With the STACK_R_ADDR at 0x600000 (6MB) we're competing with with the loading address of either u-boot or atf parts, so move that away to 0x4000000 (64MB) similar to rk3399. Only lion currently sets that at all but not sheep the second rk3368 board, so just move that to the Kconfig for rk3368 similar to rk3399 as well. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-03-30rockchip: rk3368: increase SYS_MALLOC_F_LEN to 0x4000Heiko Stuebner1-1/+1
To prevent running out of memory, increase SYS_MALLOC_F_LEN to 0x4000 similar to what rk3399 uses. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-03-30Merge tag 'v2021.04-rc5' into nextTom Rini2-1/+10
Prepare v2021.04-rc5
2021-03-27sandbox: define __dyn_sym_start, dyn_sym_endHeinrich Schuchardt1-0/+7
On RISC-V the symbols __dyn_sym_start, dyn_sym_end are referenced in efi_runtime_relocate(). Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-03-27x86: coral: Show memory config and SKU ID on startupSimon Glass1-0/+11
Provide the model information through sysinfo so that it shows up on boot. For memconfig 4 pins are provided, for 16 combinations. For SKU ID there are two options: - two pins provided in a ternary arrangement, for 9 combinations. - reading from the EC Add a binding doc and drop the unused #defines as well. Example: U-Boot 2021.01-rc5 CPU: Intel(R) Celeron(R) CPU N3450 @ 1.10GHz DRAM: 3.9 GiB MMC: sdmmc@1b,0: 1, emmc@1c,0: 2 Video: 1024x768x32 @ b0000000 Model: Google Coral (memconfig 5, SKU 3) This depends on the GPIO series: http://patchwork.ozlabs.org/project/uboot/list/?series=228126 Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
2021-03-27sandbox: Correct uninit conflictSimon Glass1-5/+1
It is not possible to remove the state before driver model is uninited, since the devices are allocated in the memory buffer. Also it is not possible to uninit driver model afterwards, since the RAM has been freed. Drop the uninit altogether, since it is not actually necessary. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27cpu: Rename SPL_CPU_SUPPORT to SPL_CPUSimon Glass4-4/+4
The _SUPPORT suffix is from an earlier time and interferes with use of the CONFIG_IS_ENABLED() macro. Rename the option to drop the suffix. Tidy up the TODO that prompted this. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27sandbox: Only delete the executable if requestedSimon Glass1-9/+15
At present sandbox removes its executable after failing to run it, since there is no other way that it would get cleaned up. However, this is actually only wanted if the image was created within sandbox. For the case where the image was generated by the build system, such as u-boot-spl, we don't want to delete it. Handle the two code paths accordingly. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27x86: coreboot: Don't setup MTRR when booting from corebootSimon Glass1-3/+3
This currently hangs and it is not necessary in any case. Drop the code when booting from coreboot. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27x86: fsp: Don't notify if booted from corebootSimon Glass1-0/+4
When booting from coreboot there is no need to notify the FSP of anything, since coreboot has already done it. Nor it is possible, since the FSP details are not provided by coreboot. Skip it in this case. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27x86: coral: Fall back to coreboot video when FSP missingSimon Glass1-0/+5
When booting from coreboot the FSP video information is no-longer available. Enable the coreboot driver so that we can get some sort of display in this case. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27x86: coral: Allow init of debug UART in U-Boot properSimon Glass4-58/+65
At present the debug UART is only set up in SPL, on the assumption that the boot flow will always pass through there. When booting from coreboot, SPL is not used, so the debug UART is not available. Move the code into a common place so that it can be used in U-Boot proper also. Add the required init to start_from_spl.S as well. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27x86: coral: Avoid build error with !CONFIG_ACPIGENSimon Glass1-5/+9
When CONFIG_ACPIGEN is not enabled the CPU code does not build. Fix this by moving things around. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27x86: fsp: Don't enable FSP graphics if booted from corebootSimon Glass1-1/+1
This driver cannot work when booted from coreboot, since the FSP information is not available. Disable it in that case, so that the coreboot video driver can be used instead. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27x86: Allow installing an e820 when booting from corebootSimon Glass5-29/+69
Move this code into a generic location so that it can be used by other x86 boards which want to boot from coreboot. Also ensure that this is called if booting from coreboot. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27x86: coreboot: Update parsing of the latest sysinfoSimon Glass3-57/+525
Quite a few new tag types have been added over the years. Bring these into U-Boot so that all required tags can be parsed. Add a proper comment to struct sysinfo_t while we are here, since many of the meanings are not obvious. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27x86: Move coreboot sysinfo parsing into generic x86 codeSimon Glass5-1/+28
It is useful to be able to parse coreboot tables on any x86 build which is booted from coreboot. Add a new Kconfig option to enable this feature and move the code so it can be used on any board, if enabled. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27x86: coreboot: Sync up timestamp codesSimon Glass2-2/+64
Add new timestamp codes that are present in coreboot, so that we can decode these in U-Boot. At present TS_U_BOOT_START_KERNEL is used twice. It should only be used just before jumping to Linux, so update the other call site to use TS_START_KERNEL. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27x86: Move coreboot timestamp info into coreboot_tables.hSimon Glass3-36/+39
This all relates to the sysinfo structure provided by coreboot. Put the timestamp definitions into the same file as the others. Tidy up a few comments at the same time. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27x86: Make coreboot sysinfo available to any x86 boardSimon Glass5-4/+4
It is possible to boot U-Boot for chromebook_coral either 'bare metal' or from coreboot. In the latter case we want to provide access to the coreboot sysinfo tables. Move the definitions into a file available to any x86 board. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27cbfs: Allow access to CBFS without a headerSimon Glass1-1/+2
In some cases CBFS does not start with a header but is just a collection of files. It is possible to support this so long as the size of the CBFS is provided. Update the cbfs_init_mem() function to support this. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27x86: coral: Update the SD card-detect GPIOSimon Glass1-1/+1
Since the recent bug fix, it doesn't matter which GPIO phandle is used so long as the GPIO number is right. Still, we may as well use the correct one to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-03-27x86: coral: Put the eMMC firstSimon Glass1-0/+1
At present the eMMC device does not have an alias so it appears after the SD card which is device 1. There is no device 0 which is odd. Make the eMMC device be the first one. Update the boot script to use the new device. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-03-27sandbox: dtsi: add rngVincent Stehlé1-0/+4
Having an rng in the sandbox is useful not only for tests but also for e.g. UEFI. Therefore, copy the rng node from test.dts to sandbox.dtsi. In the case of UEFI, it can then be verified with `efidebug dh' that a "Random Number Generator" protocol is indeed present. This also fixes the following `bootefi' error: Missing RNG device for EFI_RNG_PROTOCOL Signed-off-by: Vincent Stehlé <vincent.stehle@arm.com> Cc: Simon Glass <sjg@chromium.org>
2021-03-26x86: dts: Drop unused CONFIG_SPLSimon Glass1-5/+1
This cannot be used since the previous #elif has already dealt with SPL. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-26x86: Make use of binman expanded entriesSimon Glass1-10/+1
We don't need to spell out the separate pieces of U-Boot phase binaries anymore. Revert to using the simple entry and let binman do the expansion itself as needed. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-26x86: apl: Use read-only SPL and new of-platdataSimon Glass1-0/+2
With Apollo Lake, SPL is placed in read-only memory. Set this new option so that OF_PLATDATA_INST can be used. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-26x86: coral: Drop TPM and ACPI interrupts from TPLSimon Glass1-5/+5
These devices are not actually built in TPL but are currently active in the TPL devicetree. For of-platdata-inst this means that we will try to generate devices for them, which fails. Update them to be active only in U-Boot proper. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-26x86: Don't include reset driver in SPLSimon Glass1-1/+1
We don't normally need this driver in TPL/SPL, so drop it for now. It can be enabled by individual boards if needed. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-26x86: Support a fake PCI device with of-platdata-instSimon Glass1-0/+1
With TPL we don't need full PCI support and it adds to code size. Instead, a simple_bus driver is good enough to be able to read and write the PCI config and do a little basic setup. So at present there are two drivers in U-Boot called pci_x86. One is in UCLASS_PCI, used in SPL and U-Boot proper. The other is in UCLASS_SIMPLE_BUS and used only in TPL. Add a tag to tell dtoc about this, so it knows which one to use when generating the devices and uclasses. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-26x86: itss: Tidy up bind() for of-platdata-instSimon Glass1-2/+3
With the standard of-platdata we must fix up driver_data manually. With of-platadata-inst this is not necessary, since it is added to the device by dtoc. Update the code to handle this. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-26x86: apl: Tell of-platdata about a required header fileSimon Glass1-0/+1
This enum is needed to generate build-time devices. Tell dtoc where to find the header, to avoid compile errors in the generated code. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-26x86: apl: Fix the header order in pmcSimon Glass1-1/+1
The dm.h header should come first. In fact it needs to, since otherwise the driver model definitions are not available to dt-structs.h Fix this, since it causes problems with OF_PLATDATA_INST. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
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