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2021-03-26x86: dts: Drop unused CONFIG_SPLSimon Glass1-5/+1
This cannot be used since the previous #elif has already dealt with SPL. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-26x86: Make use of binman expanded entriesSimon Glass1-10/+1
We don't need to spell out the separate pieces of U-Boot phase binaries anymore. Revert to using the simple entry and let binman do the expansion itself as needed. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-26x86: apl: Use read-only SPL and new of-platdataSimon Glass1-0/+2
With Apollo Lake, SPL is placed in read-only memory. Set this new option so that OF_PLATDATA_INST can be used. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-26x86: coral: Drop TPM and ACPI interrupts from TPLSimon Glass1-5/+5
These devices are not actually built in TPL but are currently active in the TPL devicetree. For of-platdata-inst this means that we will try to generate devices for them, which fails. Update them to be active only in U-Boot proper. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-26x86: Don't include reset driver in SPLSimon Glass1-1/+1
We don't normally need this driver in TPL/SPL, so drop it for now. It can be enabled by individual boards if needed. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-26x86: Support a fake PCI device with of-platdata-instSimon Glass1-0/+1
With TPL we don't need full PCI support and it adds to code size. Instead, a simple_bus driver is good enough to be able to read and write the PCI config and do a little basic setup. So at present there are two drivers in U-Boot called pci_x86. One is in UCLASS_PCI, used in SPL and U-Boot proper. The other is in UCLASS_SIMPLE_BUS and used only in TPL. Add a tag to tell dtoc about this, so it knows which one to use when generating the devices and uclasses. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-26x86: itss: Tidy up bind() for of-platdata-instSimon Glass1-2/+3
With the standard of-platdata we must fix up driver_data manually. With of-platadata-inst this is not necessary, since it is added to the device by dtoc. Update the code to handle this. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-26x86: apl: Tell of-platdata about a required header fileSimon Glass1-0/+1
This enum is needed to generate build-time devices. Tell dtoc where to find the header, to avoid compile errors in the generated code. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-26x86: apl: Fix the header order in pmcSimon Glass1-1/+1
The dm.h header should come first. In fact it needs to, since otherwise the driver model definitions are not available to dt-structs.h Fix this, since it causes problems with OF_PLATDATA_INST. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-26x86: Define a region for device priv/plat dataSimon Glass1-0/+8
Collect this together in one place, so driver model can access set it up in a new place if needed. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-15Merge tag 'v2021.04-rc4' into nextTom Rini4-1/+30
Prepare v2021.04-rc4
2021-03-09x86: Select advanced Intel code only if allowedSimon Glass2-0/+16
At present most of the Intel-specific code is built on all devices, even those which don't have software support for the features provided there. This means that any board can enable CONFIG_INTEL_ACPIGEN even if it does not have the required features. Add a new INTEL_SOC option to control this access. This must be selected by SoCs that can support the required features. Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: fixed a typo in arch/x86/Kconfig] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2021-03-09x86: Move INTEL_ACPIGEN to arch/x86Simon Glass1-0/+9
This option is better placed in the x86 code since it is not generic enough to be in the core code. Move it. Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: fixed a typo in arch/x86/Kconfig] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2021-03-09x86: Fix member check in intel_gnvsSimon Glass1-0/+4
When CONFIG_CHROMEOS is not enabled this currently does not build. Fix it. Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-03-09x86: sizeof-array-div error in lpc_common_early_initHeinrich Schuchardt1-1/+1
Building qemu-x86_64_defconfig with GCC 11.0 fails with: arch/x86/cpu/intel_common/lpc.c: In function ‘lpc_common_early_init’: arch/x86/cpu/intel_common/lpc.c:56:40: error: expression does not compute the number of elements in this array; element type is ‘struct reg_info’, not ‘u32’ {aka ‘unsigned int’} [-Werror=sizeof-array-div] 56 | sizeof(values) / sizeof(u32)); | ^ arch/x86/cpu/intel_common/lpc.c:56:40: note: add parentheses around the second ‘sizeof’ to silence this warning arch/x86/cpu/intel_common/lpc.c:50:11: note: array ‘values’ declared here 50 | } values[4], *ptr; | ^~~~~~ Add parentheses to silence warning. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-03-03gpio: x86: Drop the deprecated methods in intel_gpioSimon Glass1-0/+5
We don't need to implement direction_input() and direction_output() anymore. Drop them and use update_flags() instead. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-02reset: Remove addr parameter from reset_cpu()Harald Seiler1-1/+1
Historically, the reset_cpu() function had an `addr` parameter which was meant to pass in an address of the reset vector location, where the CPU should reset to. This feature is no longer used anywhere in U-Boot as all reset_cpu() implementations now ignore the passed value. Generic code has been added which always calls reset_cpu() with `0` which means this feature can no longer be used easily anyway. Over time, many implementations seem to have "misunderstood" the existence of this parameter as a way to customize/parameterize the reset (e.g. COLD vs WARM resets). As this is not properly supported, the code will almost always not do what it is intended to (because all call-sites just call reset_cpu() with 0). To avoid confusion and to clean up the codebase from unused left-overs of the past, remove the `addr` parameter entirely. Code which intends to support different kinds of resets should be rewritten as a sysreset driver instead. This transformation was done with the following coccinelle patch: @@ expression argvalue; @@ - reset_cpu(argvalue) + reset_cpu() @@ identifier argname; type argtype; @@ - reset_cpu(argtype argname) + reset_cpu(void) { ... } Signed-off-by: Harald Seiler <hws@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-02-15Merge branch '2021-02-02-drop-asm_global_data-when-unused'Tom Rini88-7/+90
- Merge the patch to take <asm/global_data.h> out of <common.h>
2021-02-03x86: qemu: Fix broken multi-core bootBin Meng1-0/+6
Unfortunately the multi-core boot for QEMU x86 has been broken since commit 77a5e2d3bc61 ("x86: mp_init: Set up the CPU numbers at the start"). In order to support QEMU x86 multi-core boot, the /cpus node must be bound before any actual fix up in qemu_cpu_fixup(). This adds the uclass_get() call to ensure this, just like what was done before. Fixes: 77a5e2d3bc61 ("x86: mp_init: Set up the CPU numbers at the start") Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-02-02common: Drop asm/global_data.h from common headerSimon Glass88-7/+90
Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
2021-02-01x86: tpl: Show next stage being bootedSimon Glass1-1/+6
Enhance the debugging to show the next stage being booted as well as a dump of the start of the image. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-02-01x86: spl: Clear BSS unconditionallySimon Glass1-1/+1
This should be done even if not using TPL, since BSS may be in use or boards that only use SPL. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-02-01x86: zimage: Improve command-line debug handlingSimon Glass1-3/+7
At present if the command line is very long it is truncated by the printf() statement, which works within a limited buffer. Use puts() instead. Also show better debugging with the command-line setup fails. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-02-01x86: zimage: Allow dumping the image from outside the moduleSimon Glass2-8/+25
At present it is possible to dump an image within the zimage command, but it is also useful to be able to dump it from elsewhere, for example in a loader that has special handling for the different zimage stages. Export this feature as a new function. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-02-01x86: Update Chromium OS GNVS namesSimon Glass1-6/+28
The Global Non-Volatile Storage struct has some fields with particular meanings. Rename these to make things easier to follow. Also add a few more boot flags. GNVS should not be confused with GNVQ (Going Nowhere Very Quickly). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-02-01x86: spl: Make moving BSS conditionalSimon Glass1-0/+2
At present BSS is always placed in SDRAM. If a separate BSS is not in use this means that BSS doesn't work as expected. Make the setting conditional on the SEPARATE_BSS option. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-02-01x86: Make sure the SPL image ends on a suitable boundarySimon Glass1-0/+10
The part of U-Boot that actually ends up in u-boot-nodtb.bin is not built with any particular alignment. It ends at the start of the BSS section. The BSS section selects its own alignment, which may larger. This means that there can be a gap of a few bytes between the image ending and BSS starting. Since u-boot.bin is build by joining u-boot-nodtb.bin and u-boot.dtb (with perhaps some padding for BSS), the expected result is not obtained. U-Boot uses the end of BSS to find the devicetree, so this means that it cannot be found. Add 32-byte alignment of BSS so that the image size is correct and appending the devicetree will place it at the end of BSS. Example SPL output without this patch: Sections: Idx Name Size VMA LMA File off Algn 0 .text 000142a1 fef40000 fef40000 00001000 2**4 CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE 1 .u_boot_list 000014a4 fef542a8 fef542a8 000152a8 2**3 CONTENTS, ALLOC, LOAD, RELOC, DATA 2 .rodata 0000599c fef55760 fef55760 00016760 2**5 CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA 3 .data 00000970 fef5b100 fef5b100 0001c100 2**5 CONTENTS, ALLOC, LOAD, RELOC, DATA 4 .binman_sym_table 00000020 fef5ba70 fef5ba70 0001ca70 2**2 CONTENTS, ALLOC, LOAD, DATA 5 .bss 00000060 fef5baa0 fef5baa0 00000000 2**5 ALLOC You can see that .bss is aligned to 2**5 (32 bytes). This is because of the mallinfo struct in dlmalloc.c: 17 .bss.current_mallinfo 00000028 00000000 00000000 000004c0 2**5 ALLOC In this case the size of u-boot-spl-nodtb.bin is 0x1ba90. This matches up with the _image_binary_end symbol: fef5ba90 g .binman_sym_table 00000000 _image_binary_end But BSS starts 16 bytes later, at 0xfef5baa0, due to the 32-byte alignment. So we must align _image_binary_end to a 32-byte boundary. This forces the binary size to be 0x1baa0, i.e. ending at the start of bss, as expected. Note that gcc reports __BIGGEST_ALIGNMENT__ of 16 on this build, even though it generates an object file with a member that requests 32-byte alignment. The current_mallinfo struct is 40 bytes in size. Increasing the struct to 68 bytes (i.e. just above a 64-byte boundary) does not cause the alignment to go above 32 bytes. So it seems that 32 bytes is the maximum alignment at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: add more details in the commit message to help people understand] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2021-02-01x86: apl: Enhance debugging in the SPL loaderSimon Glass1-5/+7
Move to log_debug() and make use of the new SPL function to find the text base. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-02-01x86: acpi_gpe: Update driver name to match devicetreeSimon Glass1-2/+4
Use a driver name in line with the compatible string so that of-platdata can use this driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-02-01x86: coral: Add a devicetree node for eMMCSimon Glass1-0/+6
Add a node for this so we can indicate that it is does not require any ACPI code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-01-31x86: coral: Support TPM and RTC in SPLSimon Glass2-1/+22
Update the devicetree so that the TPM and RTC can be used in SPL. Also enable the pins used for getting the memory configuration settings while we are here. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-31x86: typo segementHeinrich Schuchardt2-2/+2
%s/segement/segment/ Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-01-31x86: coral: Update an unused pin to reduce powerSimon Glass1-0/+1
GPIO_25 is not used on coral, so set it up in deep sleep. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-06Merge tag 'dm-pull-5jan21' of git://git.denx.de/u-boot-dm into nextTom Rini25-135/+238
Driver model: make some udevice fields private Driver model: Rename U_BOOT_DEVICE et al. dtoc: Tidy up and add more tests ns16550 code clean-up x86 and sandbox minor fixes for of-platdata dtoc prepration for adding build-time instantiation
2021-01-06Merge tag 'v2021.01-rc5' into nextTom Rini4-13/+67
Prepare v2021.01-rc5 Signed-off-by: Tom Rini <trini@konsulko.com>
2021-01-05x86: Drop rtc from SPLSimon Glass1-1/+1
The RTC is not currently used in SPL. Drop it so that it does not take up space. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-05x86: coral: Remove unwanted nodes from SPL/TPLSimon Glass1-6/+11
Some devices are not needed in SPL/TPL. For TPL this causes the generation of unnecessary of-platadata structs. Make some adjustments to fix this. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-05x86: apl: Adjust how the UART gets its platform dataSimon Glass2-20/+42
At present this driver calls malloc() to start a new platform data structure, fills it in and tells driver model to use it. We want to avoid malloc, particularly with the new version of of-platdata. Create a new struct which encompasses both the dtd struct and the ns16550 one, to avoid this. Unfortunately we must copy the data into the right place for the ns16550 driver. Add some comments about this. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-05x86: sysreset: Move priv/plat structs to headersSimon Glass1-0/+18
With the new of-platdata, these need to be available to dt_platdata.c so must be in header files. Move them and add the dtd struct too. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2021-01-05x86: apl: Use struct spi_nor instead of struct spi_flashSimon Glass1-1/+1
This construct effectively uses struct spi_nor due to a #define in spi-nor.h so we may as well use that struct here. This allows dtoc to parse it correctly. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-05x86: Move priv/plat structs for intel_common to headersSimon Glass4-27/+40
With the new of-platdata, these need to be available to dt_platdata.c so must be in header files. Move them. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-05x86: apl: Move priv/plat structs to headersSimon Glass5-26/+64
With the new of-platdata, these need to be available to dt_platdata.c so must be in header files. Move them. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-05x86: Fix header guard in asm/pmu.hSimon Glass1-3/+3
This has the wrong name. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-05x86: tpl: Remove unwanted devicetree stringSimon Glass1-1/+3
Update this driver to use of_match_ptr(). This reduces the TPL binary size by about 32 bytes. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-05x86: apl: Reduce size for TPLSimon Glass8-11/+29
Update various drivers to use of_match_ptr() and to avoid including debug strings in TPL. Omit the WiFi driver entirely, since it is not used in TPL. This reduces the TPL binary size by about 608 bytes. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-05x86: apl: Update hostbridge to remove unwanted TPL codeSimon Glass1-5/+9
At present several strings from this file appear in the TPL binary. Add preprocessor checks to drop them. This reduces the TPL binary size by about 128 bytes. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-05x86: coral: Move fsp-m settings to a subnodeSimon Glass2-1/+9
At present these settings are in the node for host-bridge and so are visible in TPL as well as SPL. But they are only used for SPL. Move them to a subnode so that TPL does not included them. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-05x86: Move call64 into its own sectionSimon Glass1-0/+1
When this code is not used (e.g. by TPL) we want it to be excluded from the image. Put it in its own section so that this happens. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-05x86: apl: Use const for driver operationsSimon Glass2-2/+2
Update these declarations to const to ensure that the data ends up in the rodata section. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-05dm: Use access methods for dev/uclass private dataSimon Glass2-2/+3
Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-27 04:41:07 +0300