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2020-11-05x86: Add a layout for Chrome OS verified bootSimon Glass1-0/+38
Add definitions for part of the vboot context used with verified boot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-05x86: apl: Add core init for the SoCSimon Glass7-21/+170
Set up MSRs required for Apollo Lake. This enables Linux to use the timers correctly. Also write the fixed MSRs for this platform. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-05x86: Fix up driver names to avoid dtoc warningsSimon Glass9-12/+12
At present there are a lot of dtoc warnings reported when building chromebook_coral, of the form: WARNING: the driver intel_apl_lpc was not found in the driver list Correct these by using driver names that matches their compatible string. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-29x86: apl: Take advantage of the of-platdata parent supportSimon Glass1-1/+2
Now that parent devices are supported with of-platadata, we don't need the messy code to fix up the parent pointers and allocations on Apollo Lake. Put the code behind a condition. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-29x86: apl: Enable SPI flash in TPL with APL_SPI_FLASH_BOOTSimon Glass1-0/+2
At present, enabling CONFIG_APL_SPI_FLASH_BOOT does not build since SPI and SPI flash are not enabled for TPL. Add a condition to fix this and tidy up a build warning in the SPI-flash driver. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-06bloblist: Allow custom alignment for blobsSimon Glass2-2/+2
Some blobs need a larger alignment than the default. For example, ACPI tables often start at a 4KB boundary. Add support for this. Update the size of the test blob to allow these larger records. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: edison: Generate an image suitable for xFSTKSimon Glass2-0/+35
It is useful to be able to flash Edison directly without relying on the installed U-Boot being functional. Add a binman image for this. It includes a 'OSIP' header (which happens to look like an MBR / (Master-Boot Record), U-Boot binary and an environment. I am not able to find a specification for OSIP. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2020-09-25x86: Use multiple imagesSimon Glass3-21/+10
We already use binman's 'multiple-images' feature with Chrome OS and we want to use it for Edison. There is no real down-side. Adjust x86 to always use multiple-images. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2020-09-25x86: Add support for more than 8 MTRRsSimon Glass2-8/+19
At present the mtrr command only support 8 MTRRs. Some SoCs have more than that. Update the implementation to support up to 10. Read the number of MTRRs dynamically instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25x86: hob: Try to show a name instead of a GUIDSimon Glass1-0/+25
GUIDs are one of the seven evils of the computer world. They obfuscate the meaning and require people to look up long hex strings to decode it. Luckily only a miniscule fraction of the 10^38 possible GUIDs are in use. Add a way to decode the GUIDs known to U-Boot. Add a few more to the list for good measure. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25x86: coral: Update config and device tree for ACPISimon Glass1-14/+212
Enable new features and provide require device-tree config so that U-Boot produces the correct ACPI tables on Coral. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: Add a way to add to the e820 memory tableSimon Glass1-0/+17
Some boards want to reserve extra regions of memory. Add a 'chosen' property to support this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25x86: fsp: Show FSP-S or FSP-M address in fsp_get_header()Simon Glass1-8/+14
At present this function only supports FSP-M but it is also used to read FSP-S, in which case FSP-M may be zero. Add support for showing whichever address is present in the FSP binary. Also change the debug() statements to log_debug() while here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25x86: fsp: Add more debugging for silicon initSimon Glass1-1/+3
If locating the FSP header hangs for whatever reason it is useful to see where it got stuck. Add a debug print. Also show the address of the FSP-S entry point as a sanity check. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25x86: apl: Check low-level init in FSP-S pre-initSimon Glass1-0/+2
If U-Boot is not running FSP-S it should not do the pre-init either. Add a condition to handle this. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: acpi: Set the log category for x86 table generationSimon Glass1-0/+2
This file doesn't currently have a log category. Add one so that items are logged correctly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25acpi: tpm: Add a TPM1 tableSimon Glass1-1/+53
This provides information about a v1 TPM in the system. Generate this table if the TPM is present. Add a required new bloblist type and correct the header order of one header file. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25acpi: tpm: Add a TPM2 tableSimon Glass1-0/+74
This provides information about a v2 TPM in the system. Generate this table if the TPM is present. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: Correct handling of MADT table CPUsSimon Glass1-3/+6
At present if hyperthreading is disabled the CPU numbering is not sequential. Fix this. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: Add a header guard to asm/acpi_table.hSimon Glass1-0/+4
This file cannot currently be included in ASL files. Add a header guard to permit this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25x86: Correct the assembly guard in e820.hSimon Glass1-2/+1
This is currently in the wrong place, so including the file in the device tree fails. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25x86: Notify the FSP of the 'end firmware' eventSimon Glass2-0/+31
Send this notification when U-Boot is about to boot into Linux, as requested by the FSP. Currently this causes a crash with the APL FSP, so leave it disabled for now. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: Sort the MTRR tableSimon Glass1-0/+12
At present the MTRR registers are programmed with the list the U-Boot builds up in the same order. In some cases this list may be out of order. It looks better in Linux to have the registers in order, so sort them, Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: cpu: Report address width from cpu_get_info()Simon Glass4-0/+38
Add support for this new field in the common code used by most x86 CPU drivers. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: fsp: Update the FSP API with the end-firmware methodSimon Glass1-3/+12
This new method is intended to be called when UEFI shuts down the 'boot services', i.e. any lingering code in the boot loader that might be used by the OS. Add a definition for this new method and update the comments a little. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25x86: apl: Drop unnecessary code in PMC driverSimon Glass1-6/+2
We don't have CONFIG_PCI in TPL but it is present in SPL, etc. So this code is not needed. Drop it, and fix a code-style nit just above. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: apl: Generate ACPI table for LPCSimon Glass1-0/+18
Add an ACPI table for the LPC on Apollo Lake. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: apl: Generate CPU tablesSimon Glass2-1/+79
Add ACPI generation to the APL CPU driver. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: apl: Add support for hostbridge ACPI generationSimon Glass1-9/+211
Support generating a DMAR table and add a few helper routines as well. Also set up NHLT so that audio works. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: apl: Generate required ACPI tablesSimon Glass3-0/+230
Add support for generating various ACPI tables for Apollo Lake. Add a few S3 definitions that are needed. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: apl: Allow reading hostbridge base addressesSimon Glass2-0/+58
Add a few functions to permit reading of various useful base addresses provided by the hostbridge. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: acpi: Add support for additional Intel tablesSimon Glass2-0/+226
Apollo Lake needs to generate a few more table types used on Intel SoCs. Add support for these into the x86 ACPI code. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: Support Atom SoCs using SWSMISCI rather than the SWSCISimon Glass2-0/+7
Some Atom SoCs use SWSMISCI for SMI control. Add a Kconfig to select this. It is used on Apollo Lake. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: acpi: Add common Intel ACPI tablesSimon Glass6-0/+474
Add various tables that are common to Intel CPUs. These functions can be used by arch-specific CPU code. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: acpi: Add PCT and PTC tablesSimon Glass3-1/+132
These are needed for the CPU tables. Add them into an x86-specific file since we do not support them on sandbox, or include tests. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: acpi: Support generation of the DBG2 tableSimon Glass2-0/+52
Add an implementation of the DBG2 (Debug Port Table 2) ACPI table. Adjust one of the header includes to be in the correct order, before adding more. Note that the DBG2 table is generic but the PCI UART is x86-specific at present since it assumes an ns16550 UART. It can be generalised later if necessary. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: acpi: Support generation of the HPET tableSimon Glass2-0/+69
Add an implementation of the HPET (High Precision Event Timer) ACPI table. Since this is x86-specific, put it in an x86-specific file Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: Add a few common Intel CPU functionsSimon Glass2-0/+113
Add functions to query CPU information, needed for ACPI. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: apl: Update iomap for ACPISimon Glass1-0/+16
Add some more definitions to the iomap. These will be used by ACPI-generation code as well as the device tree. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: apl: Add power-management definitionsSimon Glass1-1/+39
Add SCI and power-state definitions required by ACPI tables. Fix the license to match the original source file. Als update the guard on acpi_pmc.h to avoid an error when buiding ASL. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: Add some definitions for SMMSimon Glass1-0/+27
U-Boot does not support SMM (System Management Mode) at present, but needs a few definitions to correctly set up the ACPI table. Add these. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: acpi: Add a common routine to write WiFi infoSimon Glass3-0/+129
Intel WiFi chips can use a common routine to write the information needed by linux. Add an implementation of this. Enable it for coral. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: apl: Support writing the IntelGraphicsMem tableSimon Glass6-0/+460
This table is needed by the Linux graphics driver to handle graphics correctly. Write it to ACPI. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: Add wake sources for the acpi_gpe driverSimon Glass2-0/+138
Some devices can wake the system from sleep, e.g opening the lid on a clamshell or moving a USB mouse. Add a wake to specify this for USB devices and add the settings for Apollo Lake. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: acpi: Expand the GNVSSimon Glass2-1/+2
Expand this to 4KB so that it is possible to add custom information to it. On Chromebooks this is used to pass verified-boot information. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: acpi: Support external GNVS tablesSimon Glass4-12/+34
At present U-Boot puts a magic number in the ASL for the GNVS table and searches for it later. Add a Kconfig option to use a different approach, where the ASL files declare the table as an external symbol. U-Boot can then put it wherever it likes, without any magic numbers or searching. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: Add a common global NVS structureSimon Glass2-22/+44
Add the definition of this structure common to Intel devices. It includes some optional Chrome OS pieces which are used when vboot is integrated. Drop the APL version as it is basically the same. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: Add a config for the systemagent PCIEX regions sizeSimon Glass2-0/+19
Add a way to specify the required size for this region. This is used when generating ACPI tables. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: acpi: Add DPTF asl filesSimon Glass5-0/+950
Add common DPTF (Intel Dynamic Performance and Thermal Framework) files, taken from coreboot. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: acpi: apl: Add asl files for Apollo LakeSimon Glass18-0/+1261
Add Apollo Lake ASL files, taken from coreboot. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.2.3 (git 2.39.0) at 2025-10-02 20:44:19 +0300