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2019-12-15x86: Reduce mrccache record alignment sizeSimon Glass1-1/+1
At present the records are 4KB in size. This is unnecessarily large when the SPI-flash erase size is 256 bytes. Reduce it so it will be more efficient with Apollo Lake's 24-byte variable-data record. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: spi: Add helper functions for Intel Fast SPISimon Glass2-0/+69
Most x86 CPUs use a mechanism where the SPI flash is mapped into the very top of 32-bit address space, so that it can be executed in place and read simply by copying from memory. For an 8MB ROM the mapping starts at 0xff800000. However some recent Intel CPUs do not use a simple 1:1 memory map. Instead the map starts at a different address and not all of the SPI flash is accessible through the map. This 'Fast SPI' feature requires that U-Boot check the location of the map. It is also possible (optionally) to read from the SPI flash using a driver. Add support for booting from Fast SPI. The memory-mapped version is used by both TPL and SPL on Apollo Lake. In respect of a SPI flash driver, the actual SPI driver is ich.c - this just adds a few helper functions and definitions. This is used by Apollo Lake. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15i2c: designware: Avoid using static dataSimon Glass1-0/+1
Drivers are not allowed to use static data since they may be used in SPL where BSS is not available. It is possible that driver model may provide support for numbering devices in the future. But for now, move this to global_data. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-11-03x86: Add a CPU init function for TPLSimon Glass1-0/+9
For TPL we only need to set up the features and identify the CPU to a basic level. Add a function to handle that. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-11-03x86: spl: Support init of a PUNITSimon Glass1-0/+1
The x86 power unit handles power management. Support initing this device which is modelled as a new type of system controller since there are no operations needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-11-03x86: timer: Use a separate flag for whether timer is initedSimon Glass1-0/+1
At present the value of the timer base is used to determine whether the timer has been set up or not. It is true that the timer is essentially never exactly 0 when it is read. However 'time 0' may indicate the time that the machine was reset so it is useful to be able to denote that. Update the code to use a separate flag instead. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: Add a function to set variable MTRRsSimon Glass1-0/+12
Normally U-Boot handles MTRRs through an add/commit process which overwrites all MTRRs. But in very early boot it is not desirable to clear the existing MTRRs since they may be in use and it can cause a hang. Add a new mtrr_set_next_var() function which sets up the next available MTRR to the required region. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: pass 'type' to set_var_mtrr() in mtrr_set_next_var()] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: Add new common CPU functions for turbo/burst modeSimon Glass1-0/+49
Add a few more CPU functions that are common on Intel CPUs. Also add attribution for the code source. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: add missing MSR_IA32_MISC_ENABLE write back in cpu_set_eist(); fix 2 typos in cpu_get_burst_mode_state() comments] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: Tidy up some duplicate MSR definesSimon Glass1-63/+43
Some MSR registers are defined twice in different parts of the file. Move them together and remove the duplicates. Also drop some thermal defines which are not used. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: Add common functions for TDP and perf controlSimon Glass2-1/+19
These functions are the same on modern Intel CPUs, so use common code to set them. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: return false instead of 0 in cpu_ivybridge_config_tdp_levels(); fix 'muiltiplier' and 'desgn' typos] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: Use a common bus clock for Intel CPUsSimon Glass4-9/+5
Modern Intel CPUs use a standard bus clock value of 100MHz, so put this in a common file and tidy up the copies. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: Add a common function to set CPU thermal targetSimon Glass1-0/+11
This code appears in a few places, so move it to a common file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: Use a common definition of MSR_IA32_PERF_CTLSimon Glass1-2/+0
Remove the duplicate definition as it is not needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: pci: Drop the first parameter in pci_x86_r/w_config()Simon Glass1-9/+6
This parameter is needed by the PCI driver-mode interface but is always NULL on x86. There are a number of calls to this function so it makes sense to minimise the parameters. Adjust the x86 function to omit the first parameter, and introduce stub functions to handle the conversion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/next to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: Move acpi_s3.h to a common locationSimon Glass1-130/+0
At present this hedaer is only available on x86. To allow sandbox to use it for testing, move it to a common location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: Rename turbo ratio MSR to MSR_TURBO_RATIO_LIMITSimon Glass1-2/+1
This MSR number is used on most modern Intel processors, so drop the confusing NHM prefix (which might mean Nehalem). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: drop MSR_IVT_TURBO_RATIO_LIMIT as no code uses it] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: Add various MTRR indexes and valuesSimon Glass2-0/+23
Add some new MTRRs used by Apollolake as well as a mask for the MTRR type. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: fsp: Save usable RAM and hob_list in the handoff areaSimon Glass1-0/+8
The useable RAM is calculated when the RAM is inited. Save this value so that it can be easily used in U-Boot proper. Also save a pointer to the hob list so that it is accessible (before relocation only) in U-Boot proper. This avoids having to scan it in SPL, for everything U-Boot proper might need later. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: guard handoff_arch_save() with IS_ENABLED(CONFIG_USE_HOB)] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: spl: Reduce priority of the basic SPL image loaderSimon Glass1-2/+1
This image loader works on systems where the flash is directly mapped to the last part of the 32-bit address space. On recent Intel systems (such as apollolake) this is not the case. Reduce the priority of this loader so that another one can override it. While we are here, rename the loader to BOOT_DEVICE_SPI_MMAP since BOOT_DEVICE_BOARD is not very descriptive. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: pci: Add a function to clear and set PCI config regsSimon Glass1-0/+40
At present the x86 pre-DM equivalent of pci_bus_clrset_config32() does not exist. Add it to simplify PCI init code on x86. Also add the missing functions to this header. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: Move common Intel CPU info code into a functionSimon Glass1-0/+16
Add cpu_intel_get_info() to find out the CPU info on modern Intel CPUs. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: add parameter and return value descriptions] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: fsp: Add access to variable MRC dataSimon Glass2-0/+16
With FSP2 the non-volatile storage used by the FSP to init memory can be split into a fixed piece (determined at compile time) and a variable piece (determined at run time). Add support for reading the latter. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: fsp: Add a few more definitions for FSP2Simon Glass1-1/+14
Add definitions for the FSP signature and the FSP init phase. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: Move common fsp functions into a common fileSimon Glass2-10/+17
Some of this file can be shared between FSP1 and FSP2. Move it into a shared file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: fsp: Move common dram functions into a common fileSimon Glass1-0/+9
Most of the DRAM functionality can be shared between FSP1 and FSP2. Move it into a shared file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/next to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: fsp: Tidy up comment style a littleSimon Glass3-40/+50
The comments in the FSP code use a different style from the rest of the x86 code. I am not sure it this is intentional. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: fix 2 comment style issues] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: fsp: Create a common fsp_support.h headerSimon Glass2-116/+128
Many support functions are common between FSP1 and FSP2. Add a new header to handle this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: remove forward declarations in fsp_support.h] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: Rename some FSP functions to have an fsp_ prefixSimon Glass1-3/+3
Given these exported function an fsp_ prefix since they are declared in an fsp.h header. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: Move fsp_ffs.h include to fsp_arch.hSimon Glass1-0/+1
This include file is only used for FSP v1. Avoid including it from fdt_support.h so we can use the latter with FSP v2. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: Move fsp_bootmode.h to the generic fsp directorySimon Glass2-1/+1
This header file is the same for FSP v1 and v2, although there may be some additions to come. Move it into the generic fsp directory. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: Move fsp_infoheader.h to the generic fsp directorySimon Glass2-1/+1
This header file is the same for FSP v1 and v2. Move it into the general fsp directory. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: move rename of fsp_infoheader.h from previous patch to this one] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: Move fsp_hob.h to the generic fsp directorySimon Glass2-1/+1
This header file is the same for FSP v1 and v2. Move it into the general fsp directory. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: remove inclusion of fsp_hob.h in fsp_support.h] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: Move fsp_fv.h to the generic fsp directorySimon Glass2-1/+1
This header file is the same for FSP v1 and v2. Move it into the general fsp directory. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: Move fsp_types.h to the generic fsp directorySimon Glass2-1/+1
This header file is the same for FSP v1 and v2. Move it into the general fsp directory. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: Move fsp_api.h inclusion out of fsp_support.hSimon Glass2-1/+1
This header file is different for each version of FSP. Move it into the fsp_arch.h header file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: Create a new fsp_arch.h headerSimon Glass2-2/+21
At present fsp_support.h includes fsp_vpd.h which is an FPSv1 concept (VPD means Vital Product Data). For FSPv2 only UPD (Updatable Product Data) is used. To avoid mangling header files, put these two includes in a separate header which we can adjust as necessary for FSPv2. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: Move fsp_azalia.h to the generic fsp directorySimon Glass2-2/+1
This header file is the same for FSP v1 and v2. Move it into the general fsp directory. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: remove forward declarations in fsp_support.h] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08x86: Rename existing FSP code to fsp1Simon Glass10-1/+1
Since there is now a new version of the FSP and it is incompatible with the existing version, move the code into an fsp1 directory. This will allow us to put FSP v2 code into an fsp2 directory. Add a Kconfig which defines which version is in use. Some of the code in this new fsp1/ directory is generic across both FSPv1 and FSPv2. Future patches will address this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-01x86: zImage: Propagate acpi_rsdp_addr to kernel via boot parametersAndy Shevchenko1-1/+2
This is reincarnation of the U-Boot commit 3469bf4274540d1491d58e878a9edc0bdcba17ac Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Date: Wed Jan 10 19:40:15 2018 +0200 x86: zImage: Propagate acpi_rsdp_addr to kernel via boot parameters after upstream got eventually the Linux kernel commit e6e094e053af75cbc164e950814d3d084fb1e698 Author: Juergen Gross <jgross@suse.com> Date: Tue Nov 20 08:25:29 2018 +0100 x86/acpi, x86/boot: Take RSDP address from boot params if available Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-10x86: tangier: Use spaces over TABs in ASL codeAndy Shevchenko1-13/+13
For sake of consistency use spaces over TABs in ASL code. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-10x86: tangier: Reserve PCI ECAM in motherboard resourcesAndy Shevchenko3-0/+28
Per PCI firmware specification the ACPI has to reserve the memory which is defined as PCI ECAM. Fixes: 39665beed6f7 ("x86: tangier: Enable ACPI support for Intel Tangier") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-10x86: acpi: Annotate struct acpi_table_header with __packedAndy Shevchenko1-1/+1
GCC 9.2 starts complaining about possible pointer misalignment of pointers to the unpacked (alignment=4) structures in the packed (alignment=1) ones: CC arch/x86/cpu/tangier/acpi.o arch/x86/cpu/tangier/acpi.c: In function ‘acpi_create_fadt’: arch/x86/cpu/tangier/acpi.c:22:37: warning: taking address of packed member of ‘struct acpi_fadt’ may result in an unaligned pointer value [-Waddress-of-packed-member] 22 | struct acpi_table_header *header = &(fadt->header); CC arch/x86/lib/acpi_table.o arch/x86/lib/acpi_table.c: In function ‘acpi_create_spcr’: arch/x86/lib/acpi_table.c:366:37: warning: taking address of packed member of ‘struct acpi_spcr’ may result in an unaligned pointer value [-Waddress-of-packed-member] 366 | struct acpi_table_header *header = &(spcr->header); Fix the potential issues by annotating embedded structures with __packed even though they are packed naturally. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: add GCC version number in the commit message] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-10x86: qemu: Support getting high memory sizeBin Meng1-0/+11
At present only size of memory that is below 4GiB is retrieved from QEMU. Add a function that gets size of memory that is above 4GiB. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Aiden Park <aiden.park@intel.com>
2019-09-10x86: qemu: Extract getting memory size to a separate routineBin Meng1-0/+7
This extracts getting memory size logic in dram_init() to a separate routine qemu_get_low_memory_size(). No functional changes. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Aiden Park <aiden.park@intel.com>
2019-09-10x86: acpi: Slightly reduce binary size of ACPI tables for TangierAndy Shevchenko2-3/+3
Using ACPI predefined macros, such as Zero or One, will reduce a binary size of resulting ACPI tables. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: manually fixed the conflicts when applying] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-18x86: Remove x86 specific GD flags as they are not referenced at allStefan Roese1-6/+0
This patch removes the x86 architecture specific GD flags (GD_FLG_COLD_BOOT & GD_FLG_WARM_BOOT), as they are not used. Only GD_FLG_COLD_BOOT is referenced in coreboot.c but assigned in start16.S. But the coreboot target does not use start16.S at all and boots directly from the 32-bit start code. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-08-09x86: slimbootloader: Set TSC information for tsc_timerPark, Aiden1-0/+28
Slim Bootloader already calibrated TSC and provides it to U-Boot. Therefore, U-Boot does not have to re-calibrate TSC. Configuring tsc_base and clock_rate makes x86 tsc_timer driver bypass TSC calibration and use the provided TSC frequency. - Get TSC frequency from performance info hob - Set tsc_base and clock_rate for tsc_timer driver Signed-off-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09x86: slimbootloader: Add serial driverPark, Aiden1-0/+34
Slim Bootloader provides serial port info thru its HOB list pointer. All these HOBs are eligible for Slim Bootloader based board only. - Get serial port information from the serial port info HOB - Leverage ns16550 driver with slimbootloader specific platform data Signed-off-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09x86: slimbootloader: Add memory configurationPark, Aiden1-0/+53
Slim Bootloader provides memory map info thru its HOB list pointer. Configure memory size and relocation memory from the HOB data, and provide e820 entries as well. - Get memory size from the memory map info HOB - Set available top memory lower than 4GB for U-Boot relocation - Provide e820 entries from the memory map info HOB Signed-off-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09x86: Add a common HOB libraryPark, Aiden3-219/+232
FSP (CONFIG_HAVE_FSP) and Slim Bootloader (CONFIG_SYS_SLIMBOOTLOADER) consume HOB (CONFIG_USE_HOB) data from the each HOB list pointer. Add a common HOB library in lib/hob.c and include/asm/hob.h. Signed-off-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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