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2020-10-09arm: socfpga: soc64: Add timeout waiting for NOC idle ACKChee Hong Ang1-9/+16
Add timeout waiting for NOC idle ACK during FPGA bridge disable/enable. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2020-10-09arm: socfpga: agilex: Enable FPGA Full Reconfiguration supportChee Hong Ang1-0/+1
Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM MailboxChee Hong Ang2-2/+2
Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09arm: socfpga: Use DM watchdog timerChee Hong Ang2-2/+2
All SoCFPGA platforms (except Cyclone V) are now switching to CONFIG_WDT (driver model for watchdog timer drivers) from CONFIG_HW_WATCHDOG. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09arm: socfpga: soc64: Show reset state in SPLChee Hong Ang4-0/+25
Print reset state (warm/cold) together with the source (watchdog/MPU) which has triggered the warm reset on S10 & Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09arm: socfpga: soc64: Add SDM triggered warm reset bit maskChee Hong Ang1-2/+9
Include SDM triggered warm reset bit (BIT1) in Reset Manager's stat register when checking for HPS warm reset status. Refactor the warm reset mask macro for clarity purpose. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09arm: socfpga: soc64: Initialize timer in SPL onlyChee Hong Ang1-1/+2
Timer only need to be initialized once in SPL. This patch remove the redundancy of initializing the timer again in U-Boot proper Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09arm: socfpga: soc64: Remove PHY interface setup from misc arch initChee Hong Ang1-83/+2
'dwmac_socfpga' driver will setup the PHY interface during probe. PHY interface setup in arch_misc_init() is no longer needed. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-09-03arm: socfpga: soc64: Check FPGA Config status register before bridge resetChee Hong Ang3-9/+20
Instead of querying SDM for FPGA configuration status through mailbox messages, U-Boot now checks System Manager's FPGA Config status register for FPGA configuration status before resetting bridge. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-07-01socfpga: Mark socfpga_fpga_add() as static inline in the non-FPGA caseTom Rini1-1/+1
Unless we mark the function as 'static inline' it may end up being non-inlined by the compiled and result in duplicate functions. Cc: Marek Vasut <marex@denx.de> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Vasut <marex@denx.de>
2020-06-26arm: socfpga: misc_s10: Fix EMAC register address calculationLey Foon Tan1-1/+1
Fix EMAC register address calculation, address need to multiply with sizeof(u32) or 4. This fixes write to invalid address. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-05-19common: Drop linux/bitops.h from common headerSimon Glass14-0/+19
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-19Use __ASSEMBLY__ as the assembly macrosSimon Glass4-6/+6
Some places use __ASSEMBLER__ instead which does not work since the Makefile does not define it. Fix them. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-19common: Drop linux/delay.h from common headerSimon Glass3-0/+3
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-19common: Drop log.h from common headerSimon Glass6-0/+6
Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-19command: Remove the cmd_tbl_t typedefSimon Glass2-2/+6
We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-19common: Drop init.h from common headerSimon Glass12-0/+12
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-19common: Drop net.h from common headerSimon Glass1-0/+1
Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-27arm: socfpga: stratix10: Fix incorrect CLKMGR_S10_PERPLL_BYPASS offsetLey Foon Tan1-1/+1
Offset value for CLKMGR_S10_PERPLL_BYPASS should be 0xb0, fix it. Reported-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-04-22spl: mmc: Rename spl_boot_mode() to spl_mmc_boot_mode()Harald Seiler4-4/+4
The function's name is misleading as one might think it is used generally to select the boot-mode when in reality it is only used by the MMC driver to find out in what way it should try reading U-Boot Proper from a device (either using a filesystem, a raw sector/partition, or an eMMC boot partition). Rename it to spl_mmc_boot_mode() to make it more obvious what this function is about. Link: https://lists.denx.de/pipermail/u-boot/2020-April/405979.html Signed-off-by: Harald Seiler <hws@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-04-13arm: socfpga: arria10: Enable cache driver in SPLLey Foon Tan1-0/+1
Adding "u-boot,dm-pre-reloc" and enable CONFIG_SPL_CACHE to enable cache driver in SPL. This fixed error below in SPL: cache controller driver NOT found! Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-03-31arm: socfpga: arria10: Add save_boot_params()Ley Foon Tan1-0/+32
Add save_boot_params() to save reset status value from bootrom. Bootrom will clear the status register in reset manager and stores the reset status value in shared memory. Bootrom stores shared data at last 2KB of onchip RAM. This function save reset status provided by bootrom to rst_mgr_status. More information about reset status register value can be found in reset manager register description. When running in debugger without bootrom, r0 to r3 are random values. So, skip save the value when r0 is not bootrom shared data address. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-03-31arm: socfpga: Add onchip RAM size macroLey Foon Tan2-0/+4
Add OCRAM size macro for Gen5 and Arria 10. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-03-04ARM: socfpga: Add initial support for the ABB SECU boardHolger Brunck1-0/+10
Add initial support for the ABB SECU board, which is an ArriaV-based SoCFPGA system with ethernet and booting from Denali NAND. Signed-off-by: Holger Brunck <holger.brunck@ch.abb.com> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-02-11Merge tag 'dm-pull-6feb20' of https://gitlab.denx.de/u-boot/custodians/u-boot-dmTom Rini2-0/+2
sandbox conversion to SDL2 TPM TEE driver Various minor sandbox video enhancements New driver model core utility functions
2020-02-06dm: core: Create a new header file for 'compat' featuresSimon Glass2-0/+2
At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05ddr: altera: Add DDR2 support to Gen5 driverMarek Vasut3-32/+80
Add DDR2 support to Gen5 DRAM driver. As the DDR2 macro names generated by Quartus are named differently than the DDR3 ones, use anon unions to store them in the same structures, without growing their size. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-02-03ARM: socfpga: Drop last use of socfpga_reset_managerMarek Vasut1-4/+1
This particular chunk of code was not updated, likely due to the order in which the patches were posted and applied. Fix this missing part. Fixes: bb25aca13433 ("arm: socfpga: Convert reset manager from struct to defines") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dalon Westergreen <dwesterg@gmail.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
2020-01-18common: Move hang() to the same header as panic()Simon Glass6-0/+6
At present panic() is in the vsprintf.h header file. That does not seem like an obvious choice for hang(), even though it relates to panic(). So let's put hang() in its own header. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Migrate a few more files] Signed-off-by: Tom Rini <trini@konsulko.com>
2020-01-17common: Move reset_cpu() to the CPU headerSimon Glass1-0/+1
Move this function out of common.h and into a relevant header file. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-07arm: socfpga: stratix10: Enable SMMU accessThor Thayer1-0/+7
Enable TCU access through the Stratix10 CCU so that the SMMU can access the SDRAM. Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-01-07arm: socfpga: agilex: Enable Agilex SoC buildLey Foon Tan2-0/+25
Add build support for Agilex SoC. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07arm: socfpga: agilex: Add SPL for Agilex SoCLey Foon Tan2-0/+101
Add SPL support for Agilex SoC. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07arm: agilex: Add clock handoff offset for AgilexLey Foon Tan2-4/+10
Add clock handoff offset for Agilex. Remove S10 prefix to avoid confusion. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07arm: socfpga: agilex: Add clock wrapper functionsLey Foon Tan4-0/+105
Add clock wrapper functions call to clock DM functions to get clock frequency and used in cm_print_clock_quick_summary(). Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07clk: agilex: Add clock driver for AgilexLey Foon Tan1-0/+5
Add clock manager driver for Agilex. Provides clock initialization and get_rate functions. agilex-clock.h is from Linux commit ID cd2e1ad12247. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07arm: socfpga: Fix CLKMGR_INTOSC_HZ to 400MHzLey Foon Tan1-3/+1
CLKMGR_INTOSC_HZ should be 400MHz, instead of 460MHz. Removed also unused macros CLKMGR_EOSC1_HZ and CLKMGR_FPGA_CLK_HZ. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07arm: socfpga: Move Stratix10 and Agilex clock manager common codeLey Foon Tan2-13/+26
Move Stratix10 and Agilex clock manager common code to new header file. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07arm: socfpga: agilex: Add system manager supportLey Foon Tan1-1/+2
Add system manager support for Agilex. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07arm: socfpga: Move Stratix10 and Agilex system manager common codeLey Foon Tan11-155/+158
Move Stratix10 and Agilex system manager common code to system_manager_soc64.h. Changed macros to use SYSMGR_SOC64_*. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07arm: socfpga: agilex: Add reset manager supportLey Foon Tan1-1/+2
Add reset manager support for Agilex. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07arm: socfpga: Move Stratix10 and Agilex reset manager common codeLey Foon Tan4-106/+49
Move Stratix10 and Agilex reset manager common code to reset_manager_soc64.h. Changed macros to RSTMGR_SOC64_*. Remove unused RSTMGR_XXX defines. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07arm: socfpga: Move firewall code to firewall fileLey Foon Tan4-95/+116
Move firewall related code to new firewall.c, to share code in Stratix 10 and Agilex. SDMMC will transfer data to OCRAM in SPL. So, enable privilege for SDMMC to allow DMA transfer to OCRAM. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07arm: socfpga: agilex: Add base address for Intel Agilex SoCLey Foon Tan1-0/+4
Add base address for Intel Agilex SoC. Reuse base_addr_s10.h for Agilex, only one base address is different from S10. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07arm: socfpga: Convert clock manager from struct to definesLey Foon Tan9-468/+497
Convert clock manager for Gen5, Arria 10 and Stratix 10 from struct to defines. Change to get clock manager base address from DT node instead of using #define. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07arm: socfpga: Convert system manager from struct to definesLey Foon Tan20-400/+254
Convert system manager for Gen5, Arria 10 and Stratix 10 from struct to defines. Change to get system manager base address from DT node instead of using #define. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07arm: socfpga: Convert reset manager from struct to definesLey Foon Tan13-149/+150
Convert reset manager for Gen5, Arria 10 and Stratix 10 from struct to defines. Change to get reset manager base address from DT node instead of using #define. spl_early_init() initializes the DT setup. So, move spl_early_init() to beginning of function and before get base address from DT. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-12-03common: Move some cache and MMU functions out of common.hSimon Glass2-0/+2
These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-03common: Move get_ticks() function out of common.hSimon Glass1-0/+1
This function belongs in time.h so move it over and add a comment. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-11-25ARM: socfpga: Unreset NAND in SPL on Gen5Marek Vasut1-0/+7
In case the SPL on Gen5 loads U-Boot from NAND, unreset the NAND IP explicitly in the platform code as the denali-spl driver is not aware of DM at all. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dalon Westergreen <dwesterg@gmail.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-11 13:32:38 +0300