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2021-01-18ram: aspeed: Add AST2600 DRAM control supportDylan Hung1-0/+163
AST2600 supports DDR4 SDRAM with maximum speed DDR4-1600. The DDR4 DRAM types including 128MbX16 (2Gb), 256MbX16 (4Gb), 512MbX16 (8Gb), 1GbX16 (16Gb), and 1GbX8 TwinDie (16Gb) are supported. Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com> Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2021-01-18clk: aspeed: Add AST2600 clock supportRyan Chen1-0/+338
This patch adds the clock control driver for the AST2600 SoC. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
2021-01-18acpi: Add missing ARM acpi_table headerHarm Berntsen1-0/+0
The pci_mmc.c driver can generate ACPI info and therefore includes asm/acpi_table.h by proxy. This file does not exist for the ARM architecture and thus code compilation failed when using this driver on ARM. Signed-off-by: Harm Berntsen <harm.berntsen@nedap.com> CC: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-18gpio: do not include <asm/arch/gpio.h> on ARCH_QEMUHarm Berntsen1-1/+2
As no gpio.h is defined for this architecture, to avoid compilation failure, do not include <asm/arch/gpio.h> for QEMU. Signed-off-by: Harm Berntsen <harm.berntsen@nedap.com>
2021-01-15common: board_r: Drop initr_noncached wrapperOvidiu Panait1-1/+12
Add a return value to noncached_init and use it directly in the post-relocation init sequence, rather than using a wrapper stub. Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-13Merge tag 'u-boot-amlogic-20210112' of ↵Tom Rini1-0/+4
https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic - sync amlogic GX & AXG DT to Linux 5.10 - Add new MESON_EE driver support for GXBB & AXG - Add support for Libretech-CC v2, Wetek Core2, Beelink GT-King/Pro boards - add driver for TDO tl070wsh30 panel driver - meson: isolate loading of socinfo - Add soc_rev to environment - Enable G12A support for saradc - Add correct mmcdev on VIM3(L) & Odroid-N2(C4) - Read MAC from fuses for VIM3 & VIM3L boards
2021-01-12Merge tag 'ti-v2021.04-rc1' of ↵Tom Rini1-0/+1
https://gitlab.denx.de/u-boot/custodians/u-boot-ti - DM support for OMAP PWM backlight - USB host mode support for AM654 - Minor SPI fixes - Add support k2g ice board with 1GHz silicon - Fix GTC programming for K3 devices
2021-01-12arm: ti: am33xx: add DPLL_EN_FAST_RELOCK_BYPASS macroDario Binacchi1-0/+1
Add missing DPLL_EN_FAST_RELOCK_BYPASS macro. Used to put the DPLL in idle bypass fast relock mode. Signed-off-by: Dario Binacchi <dariobin@libero.it>
2021-01-12sunxi: Add arm64 FEL supportAndre Przywara1-0/+14
So far we did not support the BootROM based FEL USB debug mode on the 64-bit builds for Allwinner SoCs: The BootROM is using AArch32, but the SPL runs in AArch64. Returning back to AArch32 was not working as expected, since the RMR reset into 32-bit mode always starts execution in the BootROM, but not in the FEL routine. After some debug and research and with help via IRC, the CPU hotplug mechanism emerged as a solution: If a certain R_CPUCFG register contains some magic, the BootROM will immediately branch to an address stored in some other register. This works well for our purposes. Enable the FEL feature by providing early AArch32 code to first save the FEL state, *before* initially entering AArch64. If we eventually determine that we should return to FEL, we reset back into AArch32, and use the CPU hotplug mechanism to run some small AArch32 code snippet that restores the initially saved FEL state. That allows the normal AArch64 SPL build to be loaded via the sunxi-fel tool, with it returning into FEL mode, so that other payloads can be transferred via FEL as well. Tested on A64, H5 and H6. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Priit Laes <plaes@plaes.org> (on Olimex A64-Olinuxino)
2021-01-12sunxi: Fix is_boot0_magic macroAndre Przywara1-2/+1
The is_boot0_magic macro is missing parentheses around the macro argument, breaking any usage with a more complex argument. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-01-12sunxi: Factor out eGON BROM header descriptionAndre Przywara1-64/+1
To be able to easily share the Allwinner eGON BROM header structure between the tools and the SPL code, move the struct definition into a separate header file. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Samuel Holland <samuel@sholland.org>
2021-01-11meson: Add soc_rev to environmentPascal Vizeli1-0/+4
Add SoC revision to environment. This can be useful to select the correct device tree at runtime (N2/N2+). Signed-off-by: Pascal Vizeli <pvizeli@syshack.ch> Signed-off-by: Stefan Agner <stefan@agner.ch> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-01-06Merge tag 'v2021.01-rc5' into nextTom Rini13-24/+34
Prepare v2021.01-rc5 Signed-off-by: Tom Rini <trini@konsulko.com>
2020-12-19dm: Avoid accessing seq directlySimon Glass1-1/+1
At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-14dm: treewide: Rename ..._platdata variables to just ..._platSimon Glass7-7/+7
Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-10armv8: lx2162a: Add Soc changes to support LX2162AMeenakshi Aggarwal5-17/+22
LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-12-09Merge tag 'u-boot-stm32-20201209' of ↵Tom Rini7-7/+7
https://gitlab.denx.de/u-boot/custodians/u-boot-stm - Manage CONFIG_ENV_EXT4_DEVICE_AND_PART in stm32mp1 board - Update ARM STI and ARM STM STM32MP Arch maintainers emails - Enable internal pull-ups for SDMMC1 on DHCOM SoM
2020-12-09treewide: Update email address Patrick Delaunay and Patrice ChotardPatrice Chotard7-7/+7
Update Patrick and my email address with the one dedicated to upstream activities. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-12-06imx8: allow overriding memory layoutMarcel Ziswiler1-0/+5
Introduce weak function board_mem_get_layout() which allows overriding the memory layout from board code in runtime, useful for handling different SKU versions. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2020-11-17sunxi: allow to use AXP20[39] attached to I2C0 on V3 seriesIcenowy Zheng1-0/+1
The reference design of Allwinner V3 series uses an AXP203 or AXP209 PMIC attached to the I2C0 bus of the SoC, although the first community-available V3s board, Lichee Pi Zero, omitted it. Allow to introduce support for the PMIC on boards with it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-11-16Merge tag 'u-boot-amlogic-20201116' of ↵Tom Rini1-92/+0
https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic - Clock fix MMC driver for SM1 based platforms - sync SOC Ids from Linux 5.10-rc1 - fix potential build warning on meson_dw_hdmi and meson-g12a-usb2 phy
2020-11-13video: rockchip: Restrict EDP, VOP, MIPI files to GPL-2.0Alper Nebi Yasak2-2/+2
These files have a lot of code in common with their counterparts in coreboot, especially in their earlier revisions: U-Boot | coreboot --------------------------------------|-------------------------------------------- drivers/video/rockchip/: | src/soc/rockchip/: - rk_edp.c (GPL-2.0+) | - common/edp.c (GPL-2.0-only) " | - rk3288/display.c (GPL-2.0-only) " | - rk3399/display.c (GPL-2.0-only) - rk_hdmi.h (GPL-2.0+) | (none) - rk_hdmi.c (GPL-2.0+) | - rk3288/hdmi.c (GPL-2.0-or-later) - rk3288_hdmi.c (GPL-2.0+) | - rk3288/hdmi.c (GPL-2.0-or-later) - rk3399_hdmi.c (GPL-2.0+) | (none) - rk_mipi.h (GPL-2.0+) | (none) - rk_mipi.c (GPL-2.0+) | - rk3399/mipi.c (GPL-2.0-only) - rk3288_mipi.c (GPL-2.0+) | - rk3399/mipi.c (GPL-2.0-only) - rk3399_mipi.c (GPL-2.0+) | - rk3399/mipi.c (GPL-2.0-only) - rk_lvds.c (GPL-2.0+) | (none) - rk_vop.h (GPL-2.0+) | (none) - rk_vop.c (GPL-2.0+) | - common/vop.c (GPL-2.0-only) - rk3288_vop.c (GPL-2.0+) | - common/vop.c (GPL-2.0-only) - rk3399_vop.c (GPL-2.0+) | (none) | arch/arm/include/asm/arch-rockchip/: | src/soc/rockchip/*/include/soc/*: - edp_rk3288.h (GPL-2.0+) | - common/.../edp.h (GPL-2.0-only) " | - rk3288/.../display.h (GPL-2.0-only) " | - rk3399/.../display.h (GPL-2.0-only) - vop_rk3288.h (GPL-2.0+) | - common/.../vop.h (GPL-2.0-only) Restrict the licenses to match coreboot's so that changes from coreboot can be imported to U-Boot as necessary. HDMI files are already 2.0+ there and rk_lvds.c has no counterpart, so keep them as is. Cc: Simon Glass <sjg@chromium.org> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Cc: Eric Gao <eric.gao@rock-chips.com> Cc: Jacob Chen <jacob-chen@iotwrt.com> Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2020-11-12mmc: meson-gx: move arch header to local headerNeil Armstrong1-92/+0
Move the asm/arch-meson/sd_emmc.h to a local meson_gx_mmc.h, remove the useless if/then and fix the meson_gx_mmc.c include. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-10-29Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqTom Rini1-1/+1
- Bug fixes and updates on vid, ls1088a lx2160a and other layerscape platforms. - Add optee_rpmb support for LX2 & Kontron sl28 support
2020-10-23Revert "arch: arm/xen: add putc() for debugging"Tom Rini1-6/+0
This reverts commit 3a51b2a2c3cedc0d2a9ce981b8e00ab8cefcb6b7. Signed-off-by: Tom Rini <trini@konsulko.com>
2020-10-23net: lx2160a.c: Update to set ECx_PMUX precedenceRazvan Ionut Cirjan1-1/+1
As per hardware documentation, ECx_PMUX has precedence over SerDes protocol. For LX2160/LX2162 if DPMACs 17 and 18 are enabled as SGMII through SerDes protocol but ECx_PMUX configured them as RGMII, then the ports will be configured as RGMII and not SGMII. Signed-off-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-10-23Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-sunxiTom Rini1-0/+1
- sun8i emac changes (Andre) - SCP firmware (Samuel)
2020-10-22arch: arm/xen: add putc() for debuggingAKASHI Takahiro1-0/+6
This new function, xen_debug_putc(), is intended to be used to enable CONFIG_DEBUG_UART on xen guest. Please note that the underlying functionality in Xen is available only when Xen is configured with !NDEBUG but is much simpler than a generic HYPERVISOR_console_io(). Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-10-22sunxi: make V3s DRAM initialization more properIcenowy Zheng1-0/+1
Previously, because we have no source code about the DRAM initialization of V3s and missing some configurations (delays and MBUS QoS info), our V3s DRAM initialization sequence is hacked from the H3 one. As the SDK shipped with PineCube contains source code for V3s libdram, we can retrieve these information from it and tweak some other magic bits. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2020-10-21arm: stm32: cleanup arch gpio.hPatrick Delaunay1-35/+2
Cosmetic update of gpio.h: - remove enumerate: stm32_gpio_port, stm32_gpio_pin because STM32_GPIO_XXX values are unused - move STM32_GPIOS_PER_BANK in stm32_gpio.c as its value is IP dependent and not arch dependent No functional change as number of banks and number of gpio by banks is managed by device tree since since DM migration and commit 8f651ca60ba1 ("pinctrl: stm32: Add get_pins_count() ops"). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-10-05phy: meson-gxl: remove invalid USB3 PHY driverNeil Armstrong1-1/+0
The registers which are managed by the meson-gxl-usb3 PHY driver are actually "USB control" registers (which are "glue" registers which manage OTG detection and routing of the OTG capable port between the DWC2 peripheral-only controller and the DWC3 host-only controller). Drop the meson-gxl-usb3 PHY driver now that the dwc3-meson-gxl-usb driver supports the USB control registers on GXL and GXM SoCs (these were previously managed by the meson-gxl-usb3 PHY driver). Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-10-05usb: dwc3: add Amlogic GXL & GXL DWC3 GlueNeil Armstrong1-0/+2
The USB support was initialy done with a set of PHYs and dwc3-of-simple because the architecture of the USB complex was not understood correctly at the time (and proper documentation was missing...). But with the G12A family, the USB complex was correctly understood and implemented correctly. This adds a proper driver for the glue, based on the G12A one, but with enough changes to require a different driver in U-Boot. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-09-17imx8mp: Remove parts MIMX8ML7 and MIMX8ML5 supportPeng Fan2-6/+1
Latest datasheet revE has removed MIMX8ML7D/5D/7C/5C parts, so update u-boot to remove decoding and support for those parts. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-09-17imx8mq: fix SSCG_PLL_REFCLK_SEL_xPeng Fan1-4/+4
Fix SSCG_PLL_REFCLK_SEL_x, the offset starts from 0, not 16 Reported-by: Coverity 3448860 Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2020-09-17imx8mq: fix FRAC_PLL_REFCLK_SEL_MASKPeng Fan1-1/+1
Coverity reported dead code, however it is FRAC_PLL_REFCLK_SEL_MASK was wrongly set. Reported-by: Coverity 10045172 Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2020-09-17imx7: ccm: correct target interface numPeng Fan1-1/+1
According to i.MX 7Dual Applications Processor Reference Manual, Rev. 1 The target interface CCM root index ranges [0,124], so the number should be 125. Reported-by: Coverity 18045 Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2020-08-26Merge tag 'u-boot-imx-20200825' of ↵Tom Rini3-4/+22
https://gitlab.denx.de/u-boot/custodians/u-boot-imx For 2020.10 ----------- - mx6: SOCs user selectable Fix for imx6q_logic Some DM conversion - mx7: introduce secondary boot device Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/720918010 Signed-off-by: Tom Rini <trini@konsulko.com>
2020-08-25Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvellTom Rini21-0/+27792
- Add basic Marvell/Cavium OcteonTX/TX2 support (Suneel) - Infrastructure changes to PCI uclass to support these SoC's (Suneel) - Add PCI, MMC & watchdog driver drivers for OcteonTX/TX2 (Suneel) - Increase CONFIG_SYS_MALLOC_F_LEN for qemu-x86 (Stefan)
2020-08-25arm: octeontx2: Add headers for OcteonTX2Suneel Garapati13-0/+25948
Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
2020-08-25arm: octeontx: Add headers for OcteonTXSuneel Garapati7-0/+1828
Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-25arm: include/asm/io.h: Add 64bit clrbits and setbits helpersSuneel Garapati1-0/+16
Add 64bit API for clrbits and setbits. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-24board: armltd: Add support for Total Compute platformUsama Arif1-1/+1
Total Compute is based on ARM architecture and has the following features enabled in u-boot: - PL011 UART - PL180 MMC - NOR Flash - FIT image with Signature - AVB Signed-off-by: Usama Arif <usama.arif@arm.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2020-08-17ARM: imx: ddr: Add deskew register programmingMarek Vasut1-3/+13
Fill is code for programming the DDR_PHY_CMD_DESKEW_CONx registers, which are optional, but can be used to fill in the byte lane delays. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
2020-08-17ARM: imx: Add support for switching primary/secondary boot mode to bmodeMarek Vasut2-0/+4
The i.MX6/i.MX7 is capable of booting a secondary "redundant" system image in case the primary one is corrupted. The user can force this boot mode as well by explicitly setting SRC GPR10 bit 30. This can be potentially useful when upgrading the bootloader itself. Expose this functionality to the user. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
2020-08-17ARM: imx: Add bmode support for iMX7Marek Vasut1-1/+5
Add the basic differentiation between i.MX6 and i.MX7 into the bmode command, the mechanism really works almost the same on both platforms. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
2020-08-14xen: Port Xen hypervisor related code from mini-osOleksandr Andrushchenko2-0/+92
Port hypervisor related code from Mini-OS. This is referencing the code of Mini-OS from [1] by Huang Shijie and Volodymyr Babchuk which is for ARM64. Update essential arch code to support required bit operations, memory barriers etc. Copyright for the bits ported belong to at least the following authors, please see related files for details: Copyright (c) 2002-2003, K A Fraser Copyright (c) 2005, Grzegorz Milos, gm281@cam.ac.uk,Intel Research Cambridge Copyright (c) 2014, Karim Allah Ahmed <karim.allah.ahmed@gmail.com> [1] - https://github.com/zyzii/mini-os.git Signed-off-by: Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com> Signed-off-by: Anastasiia Lukianenko <anastasiia_lukianenko@epam.com> [trini: Drop wmb() from musb-net/linux-compat.h now] Signed-off-by: Tom Rini <trini@konsulko.com>
2020-08-14board: Introduce xenguest_arm64 boardAndrii Anisov2-0/+29
Introduce a minimal Xen guest board running as a virtual machine under Xen Project's hypervisor [1], [2]. Part of the code is ported from Xen mini-os and also uses work initially done by different authors from NXP: please see relevant files for their copyrights. [1] https://xenbits.xen.org [2] https://wiki.xenproject.org/ Signed-off-by: Andrii Anisov <andrii_anisov@epam.com> Signed-off-by: Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com> Signed-off-by: Anastasiia Lukianenko <anastasiia_lukianenko@epam.com>
2020-08-14include/configs: aspeed: Remove hardcoded variablesChia-Wei, Wang1-0/+20
The hardcoded platform variables such as DRAM base address are not common to Aspeed SoCs AST24xx/AST25xx/AST26xx. This patch replaces those hardcoded with macros defined in a newly added header, where the basic SoC HW information are assigned accordingly. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
2020-08-04mediatek: Drop dm.h header fileSimon Glass1-1/+1
This header file should not be included in other header files. Remove it and use a forward declaration instead. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-07-29arch: arm: use dt and UCLASS_SYSCON to get gic lpi detailsRayagonda Kokatanur1-2/+2
Use device tree and UCLASS_SYSCON driver to get Generic Interrupt Controller (GIC) lpi address and maximum GIC redistributors count. Also update Kconfig to select REGMAP and SYSCON when GIC_V3_ITS is enabled. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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