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path: root/arch/arm/include/asm/armv7.h
AgeCommit message (Expand)AuthorFilesLines
2017-10-01armv7: Move L2CTLR read/write to commonJagan Teki1-0/+21
2016-07-15ARM: Add an empty secure stack sectionChen-Yu Tsai1-0/+2
2016-05-12arm/arm64: Move barrier instructions into separate headerAndre Przywara1-20/+1
2015-05-13virt-dt: Allow reservation of secure region when in a RAM carveoutJan Kiszka1-0/+1
2015-05-13ARM: Clean up CONFIG_ARMV7_NONSEC/VIRT/PSCI conditionsJan Kiszka1-2/+2
2015-04-16ARM: cpu: Add ARMv7 barrier operations supportValentine Barshak1-0/+10
2015-03-13ARM: Introduce erratum workaround for 454179Nishanth Menon1-0/+2
2015-03-13ARM: Introduce erratum workaround for 798870Nishanth Menon1-0/+3
2015-03-09ARM: PSCI: Rework the DT handler slightlyTom Rini1-1/+0
2015-03-02armv7.h: Add <asm/io.h>Tom Rini1-0/+1
2015-02-28Exynos542x: Add workaround for ARM errata 799270Akshay Saraswat1-0/+28
2015-02-28Exynos542x: Add workaround for ARM errata 798870Akshay Saraswat1-0/+16
2015-01-05ARM: bootm: do not add PSCI to fdt when booting in secure mode.Ian Campbell1-0/+1
2014-07-28ARM: HYP/non-sec/PSCI: emit DT nodesMarc Zyngier1-0/+1
2014-07-28ARM: HYP/non-sec: allow relocation to secure RAMMarc Zyngier1-3/+7
2013-10-03ARM: extend non-secure switch to also go into HYP modeAndre Przywara1-2/+4
2013-10-03ARM: add SMP support for non-secure switchAndre Przywara1-0/+1
2013-10-03ARM: add C function to switch to non-secure stateAndre Przywara1-0/+3
2013-10-03ARM: add assembly routine to switch to non-secure stateAndre Przywara1-0/+21
2013-10-03ARM: prepare armv7.h to be included from assembly sourceAndre Przywara1-1/+5
2013-07-24Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk1-17/+1
2013-03-11ARM: OMAP5: Add silicon id support for ES2.0 revision.SRICHARAN R1-0/+1
2011-11-16omap5: Add minimal support for omap5430.Sricharan1-0/+3
2011-08-03omap4: add omap4460 revision detectionAneesh V1-0/+1
2011-08-03omap4: add OMAP4430 revision checkAneesh V1-0/+5
2011-07-04armv7: cache maintenance operations for armv7Aneesh V1-0/+67
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