summaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2020-09-24arm: mvebu: clearfog: don't override set fdtfile envBaruch Siach1-0/+3
Only set the fdtfile environment variable when not already set. Fixes: 867572f09ebe6 ("ARM: mvebu: clearfog: run-time selection of DT file") Cc: Joel Johnson <mrjoel@lixil.net> Reported-by: Andre Heider <a.heider@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Andre Heider <a.heider@gmail.com>
2020-09-24arm: mvebu: defconfig: espressobin: enable NET_RANDOM_ETHADDRAndre Heider1-0/+1
The hardware does not provide a MAC address. Enable this so that network access works with just the default environment. Signed-off-by: Andre Heider <a.heider@gmail.com> Acked-by: Konstantin Porotchkin <kostap@marvell.com>
2020-09-24arm64: a37xx: increase CONFIG_SYS_BOOTM_LEN to 64MBVladimir Vid1-0/+4
Increase max gunzip size, required for booting itb recovery images on uDPU. Signed-off-by: Vladimir Vid <vladimir.vid@sartura.hr> [a.heider: adapt to mainline] Signed-off-by: Andre Heider <a.heider@gmail.com>
2020-09-24mtd: spi-nor-ids: add support for Macronix mx25u12835f flashVladimir Vid1-0/+1
Some of Marvell A3700 boards use mx25u12835f, specifically uDPU and ESPRESSObin v7. Signed-off-by: Vladimir Vid <vladimir.vid@sartura.hr> [a.heider: adapt commit message to mainline] Signed-off-by: Andre Heider <a.heider@gmail.com>
2020-09-23pci: layerscape: Fix spurious writes and panicMichael Walle1-0/+6
The fdt_fixup_pcie_ls() scans all PCI devices and assumes that all PCI root devices are layerscape PCIe controllers. Unfortunately, this is not true for the LS1028A. There is one additional static PCI root complex (this contains the networking devices) which has nothing to do with the layerscape PCIe controllers. On recent U-Boot versions this results in the following panic: "Synchronous Abort" handler, esr 0x96000044 elr: 000000009602fa04 lr : 000000009602f9f4 (reloc) elr: 00000000fbd73a04 lr : 00000000fbd739f4 x0 : 0080000002000101 x1 : 0000000000000000 x2 : 00000000fbde9000 x3 : 0000000000000001 x4 : 0000000000000000 x5 : 0000000000000030 x6 : 00000000fbdbd460 x7 : 00000000fbb3d3a0 x8 : 0000000000000002 x9 : 000000000000000c x10: 00000000ffffffe8 x11: 0000000000000006 x12: 000000000001869f x13: 0000000000000a2c x14: 00000000fbb3d2cc x15: 00000000ffffffff x16: 0000000000010000 x17: 0000000000000000 x18: 00000000fbb3fda0 x19: 0000000000000800 x20: 0000000000000000 x21: 00000001f0000000 x22: 0000000000000800 x23: 0000000000000009 x24: 00000000fbdc3c1b x25: 00000000fbdc28e5 x26: 00000000fbdcc008 x27: 00000000fbdc16e2 x28: 000000000f000000 x29: 00000000fbb3d3a0 Code: 394072a1 f94006a0 34000041 5ac00a94 (b8336814) Resetting CPU ... This bug already existed in former versions, but the spurious write was never trapped, because the destination address was a valid address (by pure luck). Make sure the PCI root is actually one of the expected PCIe layerscape controllers by matching its compatible string. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Tested-by: Heiko Thiery <heiko.thiery@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-23configs: ls1012a/ls1046a: Add CONFIG_ENV_OVERWRITE in defconfigKuldeep Singh34-0/+34
CONFIG_ENV_OVERWRITE disables write protection on various environment variables like "ethaddr" and "serial". Enable this config in LS1046A and LS1012A defconfigs. This resolves an error while setting multiple values of "ethaddr" variable. Before the change: => setenv ethaddr 00:E0:0C:00:06:0 => setenv ethaddr 00:E0:0C:00:06:1 Error: Can't overwrite "ethaddr" Error inserting "ethaddr" variable, errno=1 After the change: => setenv ethaddr 00:E0:0C:00:06:0 => setenv ethaddr 00:E0:0C:00:06:1 Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-23ls1028a: use default scan_dev_for_bootMian Yousaf Kaukab2-14/+0
scan_dev_for_efi is supposed to be called from scan_dev_for_boot. However this call is missing for ls1028ardb and ls1028aqds boards. As a result EFI boot doesn’t work. Fix this issue by removing custom definition of scan_dev_for_boot and use the default definition instead. Signed-off-by: Mian Yousaf Kaukab <ykaukab@suse.de> Reviewed-by: andy.tang@nxp.com Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-23clk: fixed-rate: Enable DM_FLAG_PRE_RELOC flagMichal Simek1-0/+1
fixed-rate driver is not different from clk_fixed_factor and it is required very early in boot that's why setup flag for it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23xilinx: zynqmp-r5: Increase amount of MALLOC spaceMichal Simek1-0/+1
There is not enough space for early allocation. That's why increase it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23cmd: pxe: Add relocation to pxe_sub cmdsT Karthik Reddy1-0/+14
pxe sub commands need to be manually relocated for architectures which enables MANUAL_RELOC as Microblaze. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-23xilinx: versal: Fix compilation error when !CONFIG_NETMichal Simek1-2/+14
PXE and DHCP shouldn't be listed when commands are not enabled that's why handle it in the same way as is done for Zynq and ZynqMP. Fixes: ec48b6c991f4 ("arm64: versal: Add support for new Xilinx Versal ACAPs") Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23xilinx: r5: Fix MPU setting for R5Michal Simek1-7/+4
Map all resource for R5 to operate properly. The patch is done based on the commit 23f7b1a77602 ("armv7R: K3: am654: Enable MPU regions") which also map the whole 4GB at first and then change mapping for DDR. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23xilinx: r5: Disable EFI loaderMichal Simek1-0/+1
Xilinx ZynqMP R5 configuration is quite minimal and there is no reason to enable EFI for it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23spl: Kconfig: Record proper dependency for SPL_ATFMichal Simek1-1/+1
ATF support was all the time based on FIT image support but this dependency is not recorded anywhere. For !SPL_FIT && SPL_ATF there is compilation error: common/spl/spl.c: In function 'board_init_r': common/spl/spl.c:689:26: error: 'struct spl_image_info' has no member named 'fdt_addr' 689 | spl_fixup_fdt(spl_image.fdt_addr); Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23xilinx: Disable CONFIG_EFI_LOADER_BOUNCE_BUFFER for ZynqMP/VersalMichal Simek2-2/+0
Both SOCs shouldn't have any problem with 64bit dma accesses. Also with PIE enabled when u-boot is placed above 4GB without any memory mapped below 4GB address space efi_memory_init() call is failing due to missing memory node. For this two reason disable this option for ZynqMP and Versal. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23mmc: zynq: Fix incorrect indentationMichal Simek1-1/+1
Trivial fix. Fixes: d1f4e39d58db ("mmc: zynq_sdhci: Add support for SD3.0" Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23fpga: zynqmp: Protect zynqmp_loads() for SPLMichal Simek1-1/+1
if conditions should match. Fixes: a18d09ea384f ("fpga: zynqmp: Add secure bitstream loading for ZynqMP") Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23fpga: kconfig: Rename SPL_FPGA_SUPPORT to SPL_FPGAMichal Simek9-20/+11
The patch does sed 's/SPL_FPGA_SUPPORT/SPL_FPGA/g' but also fixing Makefile and zynqmp.c to simplify if/endif logic in zynqmp.c. This change is mostly done to be able to use CONFIG_IS_ENABLED macro and obj-$(CONFIG_$(SPL_)FPGA) in Makefile. For them symbols need to be in sync. And removing one line from Topic Miami boards which is not needed because symbol is not enabled via Kconfig. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-23fpga: zynqmp: Get rid of ZYNQMP_SIP_SVC* macrosMichal Simek2-7/+4
There is no need to use these macros because enum pm_api_id can be used instead. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23xilinx: common: Do not save fdt_blob to bss sectionMichal Simek1-1/+1
For SPL flow without specifying address for DT loading DTB is automatically appended behind U-Boot code. Specifically _end symbol is used. Just behind it there is place for bss section. It means if early code is using static variable and there is a write to this variable DTB file is corrupted if variable is located between DTB start and end. In this particular case offset of this variable from bss section start is very small (0x40) that's why DT is currupted which breaks this boot flow. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23ARM: zynqmp: Fix SPL_DM_SPI dependenciesMichal Simek6-6/+2
Add missing dependencies for DM_SPI_FLASH. Kconfig reports it as: WARNING: unmet direct dependencies detected for SPL_DM_SPI_FLASH Depends on [n]: SPL [=n] && SPL_DM [=n] Selected by [y]: - ARCH_ZYNQMP [=y] && <choice> && SPL_DM_SPI [=y] Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23arm64: versal: Generate position-independent pre-relocation codeMichal Simek1-0/+1
Enable position independent pre-relocation to let users options to put u-boot to different locations. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23xilinx: zynqmp: Add support for saving variablesMichal Simek2-0/+39
Enabling saving variables to MMC(FAT), NAND, SPI based on primary bootmode. Maybe that logic can be tuned for more complicated use cases and better tested for different bootmodes. Tested on zcu104 to SD(FAT) and JTAG(NOWHERE). Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23xilinx: zynqmp: Get zynqmp_get_bootmode() out of CONFIG_BOARD_LATE_INITMichal Simek1-18/+18
This function will be also used by different code. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23xilinx: zynqmp: Remove one static variableMichal Simek1-3/+3
There is no reason to have name variable saved in BSS section when it doesn't need to be really used. That's why remove static from variable definition and use strdup() to duplicate string with exact size from malloc area instead. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23xilinx: zynqmp: Add missing 43/46/47dr ID codesMichal Simek1-0/+15
Add support for 43/46/47dr devices. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23xilinx: zynqmp: refactor silicon name functionIbai Erkiaga1-165/+138
Current algorithm used to get the silicon name is bit complicated and hard to follow. Updated to use more straightforward mechanism based on the Device ID code table (Table 1-2). The full IDCODE register is used (except device revision bits [31:28]) to get the device name and IDCODE2 value is used for identifying the variant. Additionally to make the algorithm bit more clear it also save some space as the devices table is slightly bit smaller. Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23xilinx: versal: Enable AXI ethernet driverAshok Reddy Soma2-2/+2
Enable AXI ethernet driver for Versal platforms. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23net: xilinx: axi_emac: Typecast flush_cache argumentsAshok Reddy Soma1-6/+6
flush_cache() arguments are not type casted to take care of 64 bit systems. Use phys_addr_t to type cast for it to work properly for 32 bit and 64 bit systems. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2020-09-23net: xilinx: axi_emac: Fix dma descriptors for 64bit and compilation warningsAshok Reddy Soma1-12/+24
There are compilation warnings showing up when we compile AXI ethernet driver for 64bit architectures. Fix them, so that it works on both 32 and 64 bit architectures. DMA descriptors are not taking care of 64bit addresses. To fix it, change axidma_bd members as below: next ==> next_desc reserverd1 ==> next_desc_msb phys ==> buf_addr reserverd2 ==> buf_addr_msb and update next_desc and buf_addr with lower 32 bits of the addresses, update next_desc_msb and buf_addr_msb with upper 32 bits of the 64bit addresses. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2020-09-23include: dt-bindings: Add MSCC headerHarini Katakam1-0/+40
Add MSCC header with delay definitions for VSC8531 and associated family devices. Signed-off-by: Harini Katakam <harini.katakam@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23arm64: zynqmp: Change bl2_plat_get_bl31_params() guardingMichal Simek1-1/+1
It was protected just for SPL_OS_BOOT but this function is only called when SPL_ATF is enabled that's why change macro name. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23nand: Kconfig: Change dependency for NAND_ARASANMichal Simek4-1/+4
NAND_ARASAN selecting DM_MTD uunconditionally. Driver can be enabled with !DM that's why Kconfig it showing it as error: WARNING: unmet direct dependencies detected for DM_MTD Depends on [n]: DM [=n] Selected by [y]: - NAND_ARASAN [=y] && MTD_RAW_NAND [=y] Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2020-09-23arm64: zynqmp: Correct value of shunt resistor for VCCINT and VCC_SOCSaeed Nowshadi1-4/+4
Value of shunt resistor for INA226s that monitor VCCINT and VCC_SOC power rails are incorrect. This patch corrects those values. Signed-off-by: Saeed Nowshadi <saeed.nowshadi@xilinx.com>
2020-09-23arm64: zynqmp: Add device tree node for 2nd mux on I2C1 busSaeed Nowshadi1-0/+25
There is 2nd pca9548 mux on I2C1 bus that controls SFP0, SFP1, and QSFP1 ports. Channel 0 and 1 are connected to J287 connector for SFP0 & SFP1, and channel 2 is connected to J288 connector for QSFP1. Signed-off-by: Saeed Nowshadi <saeed.nowshadi@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23xilinx: Enable uartlite driver for Versal/ZynqMPT Karthik Reddy2-0/+2
Add CONFIG_XILINX_UARTLITE config to versal/zynqmp defconfig to enable uartlite driver support by default. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23serial: uartlite: Add support to work with any endiannessT Karthik Reddy1-16/+48
This endinness changes are taken from linux uartlite driver. Reset TX fifo in control register and check TX fifo empty flag in lower byte of the status register to detect if it is a little endian system. Based on this check, program the registers with le32 or be32 through out the driver. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23configs: xilinx: Enable configs required for ubifsAshok Reddy Soma2-0/+5
Enable required configs for using ubifs in uboot. UBIFS testing procedure from u-boot: Let's say we have two partitions in dt as below and want to format partition1 "images" with ubifs. partition@0 { label = "boot"; reg = <0x0 0x1000000>; }; partition@1 { label = "images"; reg = <0x1000000 0x7000000>; }; We will format the partition from linux and copy some files and access from uboot later. First thing, in linux config disable CONFIG_MTD_SPI_NOR_USE_4K_SECTORS. this is required as ubifs expects min LEB size as 15*1024 bytes. Use below commands in linux to format "images" partition with ubifs. ubiformat /dev/mtd1 ubiattach /dev/ubi_ctrl -m 1 ubimkvol /dev/ubi0 -N images -m mount -t ubifs ubi0:images /mnt We can copy files to /mnt and unmount it. To access this ubifs partition from uboot, run below commands. (Don't forget to probe device before, e.g. sf probe 0 0 0) setenv mtdids "nor0=nor0" setenv mtdparts "mtdparts=nor0:16m(boot),112m(images)" ubi part images ubifsmount ubi0:images make sure we match "mtdparts" to whatever is given in dt w.r.t partition sizes. "mtdparts" command will list the mtd partitions in u-boot. Once ubifs is mounted, we can use "ubifsls" to list the files in that partition and use "ubifsload <addr> <filename>" to load files from ubifs partition to DDR. Reading information about mtd layout from DT is not supported. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23microblaze: Add support for little/big endian in/out api'sT Karthik Reddy1-6/+16
Add read/write memory utilities for 16 and 32 bits. Add these api's for both little and big endian systems similar to arm architecture. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23board: xilinx: Enable changing default DTB pick up addressMichal Simek1-1/+1
U-Boot on xilinx boards is checking one address where DTB can be placed as the first location for DTB. Originally this code was developed for Versal where QEMU was putting generated DTB for U-Boot to use. The patch enables changing this address which is necessary for cases where default address is pointing to location (DDR) which is not present. The access to this location can cause exception. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23xilinx: kconfig: Move sourcing of board Kconfig to mach foldersMichal Simek5-5/+10
Do not source xilinx board Kconfig by other boards. These configs should be available only when Xilinx platforms are selected. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23xilinx: kconfig: Change Kconfig dependencies for Xilinx driversMichal Simek3-7/+3
Zynq/ZynqMP/Versal IPs should be possible to called also from Microblaze in PL and vice versa. That's why change dependencies and do not limit enabling just for some platforms. This is follow up patch based on commit 664e16ce99a0 ("xilinx: kconfig: Change Kconfig dependencies for Xilinx drivers"). Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23env: kconfig: Add default option for ARCH_ZYNQMichal Simek1-1/+1
Zynq is similar to ZynqMP u-boot feature wise that's why also enable default option for ENV_FAT_DEVICE_AND_PART Kconfig entry. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23net: gem: Add support for more PHYs on MDIO busMichal Simek1-0/+10
Find out MDIO bus and enable MDIO access to it if this is done via different GEM controller. Only works across GEM instances. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-23xilinx: drivers: Use '_' instead of '-' in driver nameMichal Simek6-6/+6
The most of drivers are using '_' instead of '-' in driver name. That's why sync up these names to be aligned. It looks quite bad to see both in use. It is visible via dm tree command. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-23Merge tag 'mips-fixes-for-2020.10' of ↵Tom Rini8-63/+117
https://gitlab.denx.de/u-boot/custodians/u-boot-mips - mips: vocore2: fix SPL image generation - mips: vocore2: fix LZMA decompression errors - mips: vocore2: fix console output - mips: pic32mzda: fix DTC warnings and GPIO nodes - mips: pic32mzda: make GPIO and MMC working again
2020-09-23mips: vocore2: fix various issuesMauro Condarelli3-3/+5
- fix SPL image generation - fix incorrect console output - increase malloc_f and malloc_r space to fix LZMA decompression errors - increase SPI flash clock Signed-off-by: Mauro Condarelli <mc5686@mclink.it> [squashed to one patch, fix commit subject and description] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2020-09-23mips: dts: Fix PIC32MZDA GPIO register definitionsJohn Robertson1-2/+2
The GPIO bank name for banks J and K are not correct when using the 'gpio' command from the console. The driver derives the bank name from the device tree instance string by using the instance value and adding 'A': gpio0@xxaddrxx is Bank A, gpio1@yyaddryy is Bank B and so on. On the PIC32, there is no Bank I so instances 8 and 9 need to be incremented as a minimum change. An alternative (less opaque) implementation would be to use a bank-name property instead but this would require modifying the driver code too. Signed-off-by: John Robertson <john.robertson@simiatec.com>
2020-09-23mips: dts: Fix PIC32MZDA GPIO register definitionsJohn Robertson1-23/+22
GPIO state cannot be changed via the device tree (e.g. with gpio-hog) or using the 'gpio' command from the console. The root cause is a discrepancy between the driver and the device tree: the driver code expects an absolute I/O address in the <reg> property, while the device tree defines the address relative to a declaration in the parent pinctrl node. Changing the device tree to fix a driver issue would normally be wrong, however: - I have run the first version of U-Boot in which this driver appears (v2016.03) and the same problem exists, so this is not a regression; - There is no code that references a parent device tree node that might suggest the intent of the author was to parse the DT as it exists now; - The equivalent Linux PIC32 GPIO driver also uses absolute addresses for the GPIO <reg> property. This change brings the U-Boot DT more into line with Linux. Additionally, the data sheet (Microchip ref. 60001361H) shows that the register set to control a GPIO bank spans 0xE0 bytes, but the device tree specified size is only 0x48 bytes. Signed-off-by: John Robertson <john.robertson@simiatec.com>
2020-09-23mips: dts: Fix device tree warnings for PIC32MZDAJohn Robertson1-0/+11
Signed-off-by: John Robertson <john.robertson@simiatec.com>
generated by cgit v1.2.3 (git 2.39.0) at 2026-10-01 05:42:21 +0300