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2020-09-25x86: Correct handling of MADT table CPUsSimon Glass1-3/+6
At present if hyperthreading is disabled the CPU numbering is not sequential. Fix this. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: Add a header guard to asm/acpi_table.hSimon Glass1-0/+4
This file cannot currently be included in ASL files. Add a header guard to permit this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25x86: Correct the assembly guard in e820.hSimon Glass1-2/+1
This is currently in the wrong place, so including the file in the device tree fails. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25x86: Notify the FSP of the 'end firmware' eventSimon Glass2-0/+31
Send this notification when U-Boot is about to boot into Linux, as requested by the FSP. Currently this causes a crash with the APL FSP, so leave it disabled for now. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: Sort the MTRR tableSimon Glass1-0/+12
At present the MTRR registers are programmed with the list the U-Boot builds up in the same order. In some cases this list may be out of order. It looks better in Linux to have the registers in order, so sort them, Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: cpu: Report address width from cpu_get_info()Simon Glass4-0/+38
Add support for this new field in the common code used by most x86 CPU drivers. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: fsp: Update the FSP API with the end-firmware methodSimon Glass1-3/+12
This new method is intended to be called when UEFI shuts down the 'boot services', i.e. any lingering code in the boot loader that might be used by the OS. Add a definition for this new method and update the comments a little. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25tpm: cr50: Add ACPI supportSimon Glass1-0/+55
Generate ACPI information for this device so that Linux can use it correctly. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: apl: Drop unnecessary code in PMC driverSimon Glass1-6/+2
We don't have CONFIG_PCI in TPL but it is present in SPL, etc. So this code is not needed. Drop it, and fix a code-style nit just above. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: apl: Generate ACPI table for LPCSimon Glass1-0/+18
Add an ACPI table for the LPC on Apollo Lake. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: apl: Generate CPU tablesSimon Glass3-1/+80
Add ACPI generation to the APL CPU driver. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: apl: Add support for hostbridge ACPI generationSimon Glass1-9/+211
Support generating a DMAR table and add a few helper routines as well. Also set up NHLT so that audio works. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: apl: Generate required ACPI tablesSimon Glass4-0/+234
Add support for generating various ACPI tables for Apollo Lake. Add a few S3 definitions that are needed. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25p2sb: Add some definitions used for ACPISimon Glass1-0/+8
Allow this header to be included in ASL files by adding a header guard and a few definitions that are needed. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: apl: Allow reading hostbridge base addressesSimon Glass2-0/+58
Add a few functions to permit reading of various useful base addresses provided by the hostbridge. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: acpi: Add support for additional Intel tablesSimon Glass3-0/+269
Apollo Lake needs to generate a few more table types used on Intel SoCs. Add support for these into the x86 ACPI code. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: Support Atom SoCs using SWSMISCI rather than the SWSCISimon Glass2-0/+7
Some Atom SoCs use SWSMISCI for SMI control. Add a Kconfig to select this. It is used on Apollo Lake. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: acpi: Add common Intel ACPI tablesSimon Glass7-0/+483
Add various tables that are common to Intel CPUs. These functions can be used by arch-specific CPU code. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25acpi: Add more support for generating processor tablesSimon Glass3-0/+623
This adds tables relating to P-States and C-States. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: acpi: Add PCT and PTC tablesSimon Glass3-1/+132
These are needed for the CPU tables. Add them into an x86-specific file since we do not support them on sandbox, or include tests. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25acpi: Add support for generating processor tablesSimon Glass3-0/+201
ACPI has a number of CPU-related tables. Add utility functions to write out the basic packages. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: acpi: Support generation of the DBG2 tableSimon Glass4-0/+156
Add an implementation of the DBG2 (Debug Port Table 2) ACPI table. Adjust one of the header includes to be in the correct order, before adding more. Note that the DBG2 table is generic but the PCI UART is x86-specific at present since it assumes an ns16550 UART. It can be generalised later if necessary. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: acpi: Support generation of the HPET tableSimon Glass3-9/+91
Add an implementation of the HPET (High Precision Event Timer) ACPI table. Since this is x86-specific, put it in an x86-specific file Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: Add a few common Intel CPU functionsSimon Glass3-0/+125
Add functions to query CPU information, needed for ACPI. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: apl: Update iomap for ACPISimon Glass1-0/+16
Add some more definitions to the iomap. These will be used by ACPI-generation code as well as the device tree. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: apl: Add power-management definitionsSimon Glass2-3/+41
Add SCI and power-state definitions required by ACPI tables. Fix the license to match the original source file. Als update the guard on acpi_pmc.h to avoid an error when buiding ASL. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: Add some definitions for SMMSimon Glass1-0/+27
U-Boot does not support SMM (System Management Mode) at present, but needs a few definitions to correctly set up the ACPI table. Add these. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: acpi: Add a common routine to write WiFi infoSimon Glass4-0/+130
Intel WiFi chips can use a common routine to write the information needed by linux. Add an implementation of this. Enable it for coral. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: apl: Support writing the IntelGraphicsMem tableSimon Glass7-0/+461
This table is needed by the Linux graphics driver to handle graphics correctly. Write it to ACPI. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: Add wake sources for the acpi_gpe driverSimon Glass3-0/+141
Some devices can wake the system from sleep, e.g opening the lid on a clamshell or moving a USB mouse. Add a wake to specify this for USB devices and add the settings for Apollo Lake. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25i2c: Add a generic driver to generate ACPI infoSimon Glass7-0/+381
Many I2C devices produce roughly the same ACPI data with just things like the GPIO/interrupt information being different. This can be handled by a generic driver along with some information in the device tree. Add a generic i2c driver for this purpose. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
2020-09-25x86: link: Allow more space for U-BootSimon Glass1-1/+1
The extra ACPI code increases U-Boot above it current size limit. Move the start earlier to provide space. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25dm: acpi: Use correct GPIO polarity type in acpi_dp_add_gpio()Simon Glass4-6/+6
This function currently accepts the IRQ-polarity type. Fix it to use the GPIO type instead. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25acpi: Support generating a multi-function _DSM for devicesSimon Glass5-0/+335
Add a function to generate ACPI code for a _DSM method for a device. This includes functions for starting and ending each part of the _DSM. Signed-off-by: Simon Glass <sjg@chromium.org> [bmeng: fix the "new blank line at EOF" git warning] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25acpi: Add support for conditions and return valuesSimon Glass3-0/+252
Add functions to support generating ACPI code for condition checks and return values. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25acpi: Add support for writing a _PRWSimon Glass3-0/+50
A 'Power Resource for Wake' list the resources a device depends on for wake. Add a function to generate this. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: coral: Add ACPI tables for coralSimon Glass8-0/+417
This device has a large set of ACPI tables. Bring these in from coreboot so that full functionality is available (apart from SMI). Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: acpi: Expand the GNVSSimon Glass2-1/+2
Expand this to 4KB so that it is possible to add custom information to it. On Chromebooks this is used to pass verified-boot information. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: acpi: Support external GNVS tablesSimon Glass4-12/+34
At present U-Boot puts a magic number in the ASL for the GNVS table and searches for it later. Add a Kconfig option to use a different approach, where the ASL files declare the table as an external symbol. U-Boot can then put it wherever it likes, without any magic numbers or searching. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: Add a common global NVS structureSimon Glass2-22/+44
Add the definition of this structure common to Intel devices. It includes some optional Chrome OS pieces which are used when vboot is integrated. Drop the APL version as it is basically the same. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: Add a config for the systemagent PCIEX regions sizeSimon Glass2-0/+19
Add a way to specify the required size for this region. This is used when generating ACPI tables. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: apl: Correct PCIE_ECAM_BASESimon Glass1-1/+1
This value is incorrect and causes problems booting Linux. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25x86: acpi: Add DPTF asl filesSimon Glass5-0/+950
Add common DPTF (Intel Dynamic Performance and Thermal Framework) files, taken from coreboot. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: acpi: apl: Add asl files for Apollo LakeSimon Glass18-0/+1261
Add Apollo Lake ASL files, taken from coreboot. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25x86: acpi: Add base asl files for common x86 devicesSimon Glass8-5/+443
Add common x86 ASL files, taken from coreboot. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-09-25x86: acpi: Add cros_ec tablesSimon Glass10-0/+1405
Add ASL files for the Chrome OS EC, taken from coreboot. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25cros: Add information about booting Chrome OS on x86Simon Glass1-0/+32
Recent versions of Chrome OS do not have a kernel in the root disk, to save space. With the improvements to the 'zboot' command it is fairly easy to load the kernel from the raw partition. Add instructions on how to do this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25cros: Update chromium documentationSimon Glass1-3/+6
A few things have changed since this was written about 18 months ago. Update the README. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25x86: zboot: Allow overriding the command lineSimon Glass3-9/+48
When booting Chrome OS images the command line is stored separately from the kernel. Add a way to specify this address so that images boot correctly. Also add comments to the zimage.h header. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: adjust maxargs to 8 for 'zboot start'] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25x86: zboot: Add an option to dump the setup informationSimon Glass2-1/+199
There is a lot of information in the setup block and it is quite hard to decode manually. Add a 'zboot dump' command to decode it into a human-readable format. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
generated by cgit v1.2.3 (git 2.39.0) at 2026-10-01 03:58:46 +0300