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2020-10-09configs: Resync with savedefconfigTom Rini531-931/+924
Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
2020-10-09Kconfig: Create a new tools menuSimon Glass3-9/+14
At present MKIMAGE_DTC_PATH is in the devicetree menu but not within 'devicetree control' since it does not relate to that. As a result it shows up in the top menu. It actually relates to the mkimage tool, so create a new tools menu for it and move it there. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-09Kconfig: Move BOARD_TYPES under init optionsSimon Glass1-8/+8
This actually relates to something displayed on start-up, so move it into that menu. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-09Kconfig: Move BOUNCE_BUFFER under driver optionsSimon Glass2-11/+11
This option does not belong at the top level. Move it under generic driver options. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-09Kconfig: Move VERSION_VARIABLE under environmentSimon Glass2-10/+9
This relates to the environment so should not be at the top level. Move it. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-09Kconfig: MISC_INIT_R and BOARD_LATE_INIT -> start-up hooksSimon Glass1-17/+17
These are start-up hooks so put them under that menu. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-09Kconfig: Move startup hooks under init optionsSimon Glass1-31/+31
These hooks relate to U-Boot init so move them under that menu. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-09Kconfig: Create a new 'init options' menuSimon Glass1-0/+4
There are quite a few options at the top level relating to U-Boot init. Move them into their own menu. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-09Kconfig: Move DEFAULT_FDT_FILE under boot optionsSimon Glass2-5/+5
This relates to booting since it is the default devicetree provided to Linux. Move it under the 'boot options' menu. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-09Kconfig: Move SUPPORT_RAW_INITRD under boot optionsSimon Glass2-8/+8
This relates to booting, so move it under the 'boot images' menu. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-09Kconfig: Move misc boot options under 'boot options'Simon Glass2-53/+53
There are a number of miscellaneous boot images at the top level of the kconfig menu. Move these into the 'boot options' menu. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-09Kconfig: Move CONFIG_BOOTDELAY under autoboot optionsSimon Glass2-16/+16
This option relates to autoboot, so move it there. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-09Kconfig: Move autoboot options under boot optionsSimon Glass2-117/+117
At present the autoboot options are in cmd/Kconfig but they don't really relate to commands. They relate to booting, so move this menu under the boot menu. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-09Kconfig: Move boot media under boot optionsSimon Glass2-63/+63
This relates to booting, so move it under the boot menu. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-09Kconfig: Move boot timing under boot optionsSimon Glass2-291/+291
This relates to booting, so move it under the boot menu. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-09Kconfig: Move boot menu into common/Simon Glass3-341/+342
Most of the boot options are in common/Kconfig but that file is already extremely large. Create a new Kconfig.boot to hold the boot options. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-09Kconfig: Add a 'Boot options' menuSimon Glass1-0/+4
There are quite a few boot-related menu options at the top level. Create a new menu to hold these and move 'Boot images' into it. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-09Merge branch '2020-10-08-misc-board-improvements'Tom Rini37-303/+2171
- Move ASPEED ram driver, update. - Exhance pinctrl/gpio support, update Kendryte K210 support - Enhance qemu_arm64 support for a single binary to work with and without TF-A
2020-10-09Makefile: socfpga: Generate sfp file with 4 SPL imagesChee Hong Ang1-9/+18
Generate 'u-boot-splx4.sfp' which consist of 4 SPL images required for booting up Cyclone5/Arria10. By default, this 'u-boot-splx4.sfp' is generated without extra padding after each SPL image. For Cyclone5, 'u-boot-splx4.sfp' contains: 4 x SPL(64KB) = 256KB For Arria10, 'u-boot-splx4.sfp' contains: 4 x SPL(256KB) = 1024KB For Cyclone5 using NAND flash image layout for 128 KB memory blocks, user can 'make' the following target to generate 4 SPL images with padding: make u-boot-spl-padx4.sfp 'u-boot-spl-padx4.sfp' contains four 128KB SPL images (each 64KB SPL is followed by 64KB of zero-padding). 4 x (SPL(64KB) + zero-padding(64KB)) = 512KB Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09arm: socfpga: soc64: Remove CONFIG_OF_EMBEDChee Hong Ang2-2/+0
CONFIG_OF_EMBED was primarily enabled to support the S10/Agilex spl hex file requirements. Since this option now produces a warning during build, and the spl hex can be created using alternate methods, CONFIG_OF_EMBED is no longer needed. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2020-10-09tools: socfpgaimage: Add param entry point (ep) support for Arria 10 (v1)Ley Foon Tan1-8/+13
Add param entry point (ep) support for Arria 10 header. User can pass in 'e' option to mkimage to set the entry point. This is an optional option. If not specified, default is 0x14. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09tools: socfpgaimage: Add check params function for Arria 10 (v1)Ley Foon Tan1-3/+26
Add check params function for Arria 10 (header v1). From [1] page 42, entry point offset should be 4 bytes aligned and any value smaller than 0x14 is invalid. Rename existing socfpgaimage_check_params() for v0. [1]: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_soc_eds.pdf Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09arm: dts: socfpga: arria10: Move to use generic handoff dtsiLey Foon Tan3-330/+292
Move to use generic handoff dtsi (socfpga_arria10-handoff.dtsi) and include the specify generated _handoff.h header file from qts-filter-a10.sh script. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09arm: socfpga: arria10: Add handoff header for A10 SoCDK SDMMCDalon Westergreen1-0/+305
Add the qts-filter-a10.sh generated handoff header file for the Arria10 SoCDK SDMMC u-boot device tree. Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09arm: socfpga: arria10: Add qts-filter for Arria10 socfpgaDalon Westergreen2-4/+174
Add a script to process HPS handoff data and generate a header for inclusion in u-boot specific devicetree addons. The header should be included in the top level of u-boot.dtsi. Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09arm: socfpga: soc64: Disable CONFIG_PSCI_RESETChee Hong Ang2-0/+2
Don't invoke 'SYSTEM_RESET' PSCI function because PSCI function calls are not supported by u-boot running in EL3. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09arm: socfpga: mailbox: Add mailbox retry supportLey Foon Tan1-9/+31
Resend mailbox command for 3 times with 2ms interval in between if it receives MBOX_RESP_TIMEOUT and MBOX_RESP_DEVICE_BUSY response code. Add a wrapper function mbox_send_cmd_common_retry() for retry, change all the callers to use this wrapper function. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2020-10-09arm: socfpga: mailbox: Update mailbox response codesLey Foon Tan1-2/+36
Sync latest mailbox response codes from SDM firmware. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2020-10-09arm: socfpga: mailbox: Support sending large mailbox commandChee Hong Ang1-35/+78
Mailbox command which is too large to fit into the mailbox FIFO command buffer can be sent to SDM in multiple parts. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09arm: socfpga: mailbox: Always read mailbox responses before returning statusChee Hong Ang1-4/+2
Mailbox driver should always check for the length of the response and read the response data before returning the response status to caller. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09arm: socfpga: mailbox: Refactor mailbox timeout event handlingChee Hong Ang1-4/+9
Add miliseconds delay when waiting for mailbox event to happen before timeout. This will ensure the timeout duration is predictive. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09arm: socfpga: soc64: Document down boot_scratch_cold register usageChin Liang See1-0/+8
Document down the usage of boot_scratch_cold register to avoid overlapping of usage in the code for S10 & Agilex. The boot_scratch_cold register is generally used for passing critical system info between SPL, U-Boot and Linux. Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09arm: socfpga: soc64: Add timeout waiting for NOC idle ACKChee Hong Ang1-9/+16
Add timeout waiting for NOC idle ACK during FPGA bridge disable/enable. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2020-10-09arm: socfpga: agilex: Enable FPGA Full Reconfiguration supportChee Hong Ang2-1/+2
Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09fpga: intel_sdm_mb: Add watchdog resetChee Hong Ang1-0/+3
Ensure watchdog reset is not triggered if the fpga reconfiguration is taking too long. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM MailboxChee Hong Ang7-17/+19
Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09arm: socfpga: Use DM watchdog timerChee Hong Ang7-3/+13
All SoCFPGA platforms (except Cyclone V) are now switching to CONFIG_WDT (driver model for watchdog timer drivers) from CONFIG_HW_WATCHDOG. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09arm: socfpga: soc64: Show reset state in SPLChee Hong Ang4-0/+25
Print reset state (warm/cold) together with the source (watchdog/MPU) which has triggered the warm reset on S10 & Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09arm: socfpga: soc64: Add SDM triggered warm reset bit maskChee Hong Ang1-2/+9
Include SDM triggered warm reset bit (BIT1) in Reset Manager's stat register when checking for HPS warm reset status. Refactor the warm reset mask macro for clarity purpose. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09sysreset: socfpga: agilex: Enable sysreset supportChee Hong Ang2-2/+2
Enable sysreset support for Agilex platform. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09sysreset: socfpga: soc64: Rename SYSRESET SoCFPGA driver for S10 to SoC64Chee Hong Ang4-5/+5
Rename the driver from S10 to SoC64 because Intel Agilex platform also using the this SYSRESET SoCFPGA driver for S10. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09configs: socfpga: soc64: Avoid SPL enter infinite loop during exceptionChin Liang See2-0/+2
In current implementation, any exception would trigger a CPU reset. But a bad written SPL would cause infinite loop where the system will reload the same SPL instead of loading factory safe image. Hence this patch is to ensure any exception will cause a hang. At this moment, watchdog shall be triggered and Remote System Update mechanism shall load the next production image or factory safe image. Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09arm: socfpga: soc64: Initialize timer in SPL onlyChee Hong Ang1-1/+2
Timer only need to be initialized once in SPL. This patch remove the redundancy of initializing the timer again in U-Boot proper Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09arm: socfpga: soc64: Remove PHY interface setup from misc arch initChee Hong Ang1-83/+2
'dwmac_socfpga' driver will setup the PHY interface during probe. PHY interface setup in arch_misc_init() is no longer needed. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09clk: agilex: Additional membus writes for HPS PLLChee Hong Ang1-16/+78
Add additional membus writes to configure main and peripheral PLL for Agilex's clock manager. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09clk: agilex: Handle clock configuration differently in SPL and U-Boot properChee Hong Ang1-0/+10
Since warm reset may optionally set the CLock Manager to'boot mode', the clock driver should always force the Agilex's Clock Manager to 'boot mode' before the clock driver start configuring the Clock Manager in SPL. In SSBL, clock driver will skip the Clock Manager configuration if it's already being setup by SPL (Clock Manager NOT in 'boot mode') to prevent any inaccurate clocking issues happened on HPS peripherals such as UART, MAC and etc. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2020-10-09clk: agilex: Add clock enable supportLey Foon Tan1-0/+6
Some drivers probing failed if clock enable function is not supported in clock driver. So, add clock enable function to clock driver to solve it. Return 0 (success) for *.enable function because all clocks are enabled by default in clock driver probe. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2020-10-09clk: agilex: Add NAND clock supportLey Foon Tan1-0/+3
Add get nand_clk and nand_x clock support. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2020-10-08qemu-arm64: Enable POSITION_INDEPENDENTAndre Przywara2-0/+2
Now that PIE works when U-Boot is started from ROM, let's enable CONFIG_POSITION_INDEPENDENT, which allows to load U-Boot also via ARM Trusted-Firmware's fip.bin to DRAM, without tweaking the configuration. To get a writable initial stack, we need to keep the fixed initial stack pointer, which points to DRAM in our case. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2020-10-08qemu-arm: Drop ARCH_SUPPORT_TFABOOTAndre Przywara1-1/+0
CONFIG_ARCH_SUPPORT_TFABOOT was used on the qemu-arm64 platform to guard a tweak to the flash bank configuration. U-Boot now reads the current flash setup from the devicetree, so there is no need for this option anymore. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Tom Rini <trini@konsulko.com>
generated by cgit v1.2.3 (git 2.39.0) at 2026-10-01 09:39:30 +0300